mirror of
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Properly emit range comparisons for switch cases, where neighbour cases
go to the same destination. Now we're producing really good code for switch-lower-feature.ll testcase git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35672 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
bbf6f5751d
commit
5502bf67cd
@ -15,6 +15,8 @@
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#define LLVM_ADT_BITVECTOR_H
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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#include <cstdlib>
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namespace llvm {
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@ -82,15 +82,17 @@ public:
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/// SDISel for the code generation of additional basic blocks needed by multi-
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs,
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me)
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: CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs),
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit.
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Value *CmpLHS, *CmpRHS;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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@ -12,9 +12,11 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Constants.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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@ -358,11 +360,26 @@ class SelectionDAGLowering {
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/// analysis.
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std::vector<SDOperand> PendingLoads;
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/// Case - A pair of values to record the Value for a switch case, and the
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/// case's target basic block.
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typedef std::pair<Constant*, MachineBasicBlock*> Case;
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typedef std::vector<Case>::iterator CaseItr;
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typedef std::pair<CaseItr, CaseItr> CaseRange;
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/// Case - A struct to record the Value for a switch case, and the
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/// case's target basic block.
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struct Case {
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Constant* Low;
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Constant* High;
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MachineBasicBlock* BB;
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Case() : Low(0), High(0), BB(0) { }
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Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
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Low(low), High(high), BB(bb) { }
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uint64_t size() const {
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uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
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uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
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return (rHigh - rLow + 1ULL);
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}
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};
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typedef std::vector<Case> CaseVector;
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typedef CaseVector::iterator CaseItr;
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typedef std::pair<CaseItr, CaseItr> CaseRange;
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/// CaseRec - A struct with ctor used in lowering switches to a binary tree
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/// of conditional branches.
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@ -382,15 +399,21 @@ class SelectionDAGLowering {
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};
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typedef std::vector<CaseRec> CaseRecVector;
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/// The comparison function for sorting Case values.
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/// The comparison function for sorting the switch case values in the vector.
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/// WARNING: Case ranges should be disjoint!
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struct CaseCmp {
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bool operator () (const Case& C1, const Case& C2) {
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assert(isa<ConstantInt>(C1.first) && isa<ConstantInt>(C2.first));
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return cast<const ConstantInt>(C1.first)->getSExtValue() <
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cast<const ConstantInt>(C2.first)->getSExtValue();
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bool operator () (const Case& C1,
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const Case& C2) {
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assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
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const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
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const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
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return CI1->getValue().slt(CI2->getValue());
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}
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};
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unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
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public:
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// TLI - This is information that describes the available target features we
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@ -912,14 +935,14 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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}
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SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
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BOp->getOperand(1), TBB, FBB, CurBB);
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BOp->getOperand(1), NULL, TBB, FBB, CurBB);
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SwitchCases.push_back(CB);
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return;
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}
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// Create a CaseBlock record representing this branch.
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SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
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TBB, FBB, CurBB);
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NULL, TBB, FBB, CurBB);
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SwitchCases.push_back(CB);
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return;
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}
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@ -1058,7 +1081,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
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// Create a CaseBlock record representing this branch.
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SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
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Succ0MBB, Succ1MBB, CurMBB);
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NULL, Succ0MBB, Succ1MBB, CurMBB);
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// Use visitSwitchCase to actually insert the fast branch sequence for this
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// cond branch.
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visitSwitchCase(CB);
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@ -1070,16 +1093,36 @@ void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
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SDOperand Cond;
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SDOperand CondLHS = getValue(CB.CmpLHS);
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// Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
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// handle common cases produced by branch lowering.
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if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
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Cond = CondLHS;
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else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
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SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
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Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
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} else
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Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
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// Build the setcc now.
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if (CB.CmpMHS == NULL) {
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// Fold "(X == true)" to X and "(X == false)" to !X to
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// handle common cases produced by branch lowering.
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if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
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Cond = CondLHS;
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else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
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SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
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Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
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} else
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Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
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} else {
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assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
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uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
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uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
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SDOperand CmpOp = getValue(CB.CmpMHS);
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MVT::ValueType VT = CmpOp.getValueType();
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if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
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Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
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} else {
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SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
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Cond = DAG.getSetCC(MVT::i1, SUB,
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DAG.getConstant(High-Low, VT), ISD::SETULE);
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}
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}
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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MachineBasicBlock *NextBlock = 0;
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@ -1218,7 +1261,7 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) {
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void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
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}
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/// handleSmaaSwitchCaseRange - Emit a series of specific tests (suitable for
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/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
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/// small case ranges).
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bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
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CaseRecVector& WorkList,
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@ -1230,7 +1273,7 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
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unsigned Size = CR.Range.second - CR.Range.first;
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if (Size >=3)
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return false;
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// Get the MachineFunction which holds the current MBB. This is used when
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// inserting any additional MBBs necessary to represent the switch.
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MachineFunction *CurMF = CurMBB->getParent();
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@ -1248,11 +1291,11 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
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// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
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// Rearrange the case blocks so that the last one falls through if possible.
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if (NextBlock && Default != NextBlock && BackCase.second != NextBlock) {
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if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
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// The last case block won't fall through into 'NextBlock' if we emit the
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// branches in this order. See if rearranging a case value would help.
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for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
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if (I->second == NextBlock) {
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if (I->BB == NextBlock) {
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std::swap(*I, BackCase);
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break;
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}
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@ -1272,9 +1315,19 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
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// If the last case doesn't match, go to the default block.
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FallThrough = Default;
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}
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SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, I->first,
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I->second, FallThrough, CurBlock);
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Value *RHS, *LHS, *MHS;
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ISD::CondCode CC;
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if (I->High == I->Low) {
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// This is just small small case range :) containing exactly 1 case
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CC = ISD::SETEQ;
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LHS = SV; RHS = I->High; MHS = NULL;
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} else {
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CC = ISD::SETLE;
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LHS = I->Low; MHS = SV; RHS = I->High;
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}
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SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
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I->BB, FallThrough, CurBlock);
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// If emitting the first comparison, just call visitSwitchCase to emit the
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// code into the current block. Otherwise, push the CaseBlock onto the
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@ -1302,18 +1355,27 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
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// Size is the number of Cases represented by this range.
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unsigned Size = CR.Range.second - CR.Range.first;
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uint64_t First = cast<ConstantInt>(FrontCase.first)->getSExtValue();
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uint64_t Last = cast<ConstantInt>(BackCase.first)->getSExtValue();
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int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
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int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
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uint64_t TSize = 0;
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for (CaseItr I = CR.Range.first, E = CR.Range.second;
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I!=E; ++I)
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TSize += I->size();
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if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) &&
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!TLI.isOperationLegal(ISD::BRIND, MVT::Other)) ||
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Size <= 5)
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return false;
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double Density = (double)Size / (double)((Last - First) + 1ULL);
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if (Density < 0.3125)
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double Density = (double)TSize / (double)((Last - First) + 1ULL);
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if (Density < 0.4)
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return false;
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DOUT << "Lowering jump table\n"
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<< "First entry: " << First << ". Last entry: " << Last << "\n"
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<< "Size: " << TSize << ". Density: " << Density << "\n";
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// Get the MachineFunction which holds the current MBB. This is used when
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// inserting any additional MBBs necessary to represent the switch.
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MachineFunction *CurMF = CurMBB->getParent();
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@ -1342,19 +1404,21 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
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// the default BB.
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std::vector<MachineBasicBlock*> DestBBs;
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int64_t TEI = First;
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for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI)
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if (cast<ConstantInt>(I->first)->getSExtValue() == TEI) {
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DestBBs.push_back(I->second);
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++I;
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for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
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int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
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int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
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if ((Low <= TEI) && (TEI <= High)) {
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DestBBs.push_back(I->BB);
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if (TEI==High)
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++I;
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} else {
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DestBBs.push_back(Default);
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}
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}
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// Update successor info. Add one edge to each unique successor.
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// Vector bool would be better, but vector<bool> is really slow.
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std::vector<unsigned char> SuccsHandled;
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SuccsHandled.resize(CR.CaseBB->getParent()->getNumBlockIDs());
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BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
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for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
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E = DestBBs.end(); I != E; ++I) {
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if (!SuccsHandled[(*I)->getNumber()]) {
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@ -1404,30 +1468,38 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
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// Size is the number of Cases represented by this range.
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unsigned Size = CR.Range.second - CR.Range.first;
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uint64_t First = cast<ConstantInt>(FrontCase.first)->getSExtValue();
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uint64_t Last = cast<ConstantInt>(BackCase.first)->getSExtValue();
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int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
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int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
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double Density = 0;
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CaseItr Pivot;
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CaseItr Pivot = CR.Range.first + Size/2;
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// Select optimal pivot, maximizing sum density of LHS and RHS. This will
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// (heuristically) allow us to emit JumpTable's later.
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unsigned LSize = 1;
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unsigned RSize = Size-1;
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uint64_t TSize = 0;
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for (CaseItr I = CR.Range.first, E = CR.Range.second;
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I!=E; ++I)
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TSize += I->size();
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uint64_t LSize = FrontCase.size();
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uint64_t RSize = TSize-LSize;
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for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
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J!=E; ++I, ++J, ++LSize, --RSize) {
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uint64_t LEnd = cast<ConstantInt>(I->first)->getSExtValue();
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uint64_t RBegin = cast<ConstantInt>(J->first)->getSExtValue();
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J!=E; ++I, ++J) {
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int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
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int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
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double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
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double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
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if (Density < (LDensity + RDensity)) {
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Pivot = J;
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Density = LDensity + RDensity;
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}
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LSize += J->size();
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RSize -= J->size();
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}
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CaseRange LHSR(CR.Range.first, Pivot);
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CaseRange RHSR(Pivot, CR.Range.second);
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Constant *C = Pivot->first;
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Constant *C = Pivot->Low;
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MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
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// We know that we branch to the LHS if the Value being switched on is
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@ -1437,10 +1509,10 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
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// Pivot's Value, then we can branch directly to the LHS's Target,
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// rather than creating a leaf node for it.
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if ((LHSR.second - LHSR.first) == 1 &&
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LHSR.first->first == CR.GE &&
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cast<ConstantInt>(C)->getZExtValue() ==
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(cast<ConstantInt>(CR.GE)->getZExtValue() + 1ULL)) {
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TrueBB = LHSR.first->second;
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LHSR.first->High == CR.GE &&
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cast<ConstantInt>(C)->getSExtValue() ==
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(cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
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TrueBB = LHSR.first->BB;
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} else {
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TrueBB = new MachineBasicBlock(LLVMBB);
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CurMF->getBasicBlockList().insert(BBI, TrueBB);
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@ -1452,9 +1524,9 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
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// is CR.LT - 1, then we can branch directly to the target block for
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// the current Case Value, rather than emitting a RHS leaf node for it.
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if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
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cast<ConstantInt>(RHSR.first->first)->getZExtValue() ==
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(cast<ConstantInt>(CR.LT)->getZExtValue() - 1ULL)) {
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FalseBB = RHSR.first->second;
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cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
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(cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
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FalseBB = RHSR.first->BB;
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} else {
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FalseBB = new MachineBasicBlock(LLVMBB);
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CurMF->getBasicBlockList().insert(BBI, FalseBB);
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@ -1464,8 +1536,8 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
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// Create a CaseBlock record representing a conditional branch to
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// the LHS node if the value being switched on SV is less than C.
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// Otherwise, branch to LHS.
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SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, TrueBB, FalseBB,
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CR.CaseBB);
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SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
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TrueBB, FalseBB, CR.CaseBB);
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if (CR.CaseBB == CurMBB)
|
||||
visitSwitchCase(CB);
|
||||
@ -1475,16 +1547,57 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
|
||||
return true;
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
|
||||
// Clusterify - Transform simple list of Cases into list of CaseRange's
|
||||
unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
|
||||
const SwitchInst& SI) {
|
||||
unsigned numCmps = 0;
|
||||
|
||||
// Start with "simple" cases
|
||||
for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
|
||||
MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
|
||||
Cases.push_back(Case(SI.getSuccessorValue(i),
|
||||
SI.getSuccessorValue(i),
|
||||
SMBB));
|
||||
}
|
||||
sort(Cases.begin(), Cases.end(), CaseCmp());
|
||||
|
||||
// Merge case into clusters
|
||||
if (Cases.size()>=2)
|
||||
for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) {
|
||||
int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
|
||||
int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
|
||||
MachineBasicBlock* nextBB = J->BB;
|
||||
MachineBasicBlock* currentBB = I->BB;
|
||||
|
||||
// If the two neighboring cases go to the same destination, merge them
|
||||
// into a single case.
|
||||
if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
|
||||
I->High = J->High;
|
||||
J = Cases.erase(J);
|
||||
} else {
|
||||
I = J++;
|
||||
}
|
||||
}
|
||||
|
||||
for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
|
||||
if (I->Low != I->High)
|
||||
// A range counts double, since it requires two compares.
|
||||
++numCmps;
|
||||
}
|
||||
|
||||
return numCmps;
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
|
||||
// Figure out which block is immediately after the current one.
|
||||
MachineBasicBlock *NextBlock = 0;
|
||||
MachineFunction::iterator BBI = CurMBB;
|
||||
|
||||
MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
|
||||
MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
|
||||
|
||||
// If there is only the default destination, branch to it if it is not the
|
||||
// next basic block. Otherwise, just fall through.
|
||||
if (I.getNumOperands() == 2) {
|
||||
if (SI.getNumOperands() == 2) {
|
||||
// Update machine-CFG edges.
|
||||
|
||||
// If this is not a fall-through branch, emit the branch.
|
||||
@ -1499,18 +1612,15 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
|
||||
// If there are any non-default case statements, create a vector of Cases
|
||||
// representing each one, and sort the vector so that we can efficiently
|
||||
// create a binary search tree from them.
|
||||
std::vector<Case> Cases;
|
||||
CaseVector Cases;
|
||||
unsigned numCmps = Clusterify(Cases, SI);
|
||||
DOUT << "Clusterify finished. Total clusters: " << Cases.size()
|
||||
<< ". Total compares: " << numCmps << "\n";
|
||||
|
||||
for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
|
||||
MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
|
||||
Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
|
||||
}
|
||||
std::sort(Cases.begin(), Cases.end(), CaseCmp());
|
||||
|
||||
// Get the Value to be switched on and default basic blocks, which will be
|
||||
// inserted into CaseBlock records, representing basic blocks in the binary
|
||||
// search tree.
|
||||
Value *SV = I.getOperand(0);
|
||||
Value *SV = SI.getOperand(0);
|
||||
|
||||
// Push the initial CaseRec onto the worklist
|
||||
CaseRecVector WorkList;
|
||||
|
||||
47
test/CodeGen/Generic/switch-lower-feature-2.ll
Normal file
47
test/CodeGen/Generic/switch-lower-feature-2.ll
Normal file
@ -0,0 +1,47 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep jb | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep \$6 | wc -l | grep 2 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep 1024 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep 1023 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep 119 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep JTI | wc -l | grep 2 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep jg | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep ja | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep js | wc -l | grep 1
|
||||
|
||||
define i32 @main(i32 %tmp158) {
|
||||
entry:
|
||||
switch i32 %tmp158, label %bb336 [
|
||||
i32 -2147483648, label %bb338
|
||||
i32 -2147483647, label %bb338
|
||||
i32 -2147483646, label %bb338
|
||||
i32 120, label %bb338
|
||||
i32 121, label %bb339
|
||||
i32 122, label %bb340
|
||||
i32 123, label %bb341
|
||||
i32 124, label %bb342
|
||||
i32 125, label %bb343
|
||||
i32 126, label %bb336
|
||||
i32 1024, label %bb338
|
||||
i32 0, label %bb338
|
||||
i32 1, label %bb338
|
||||
i32 2, label %bb338
|
||||
i32 3, label %bb338
|
||||
i32 4, label %bb338
|
||||
i32 5, label %bb338
|
||||
]
|
||||
bb336:
|
||||
ret i32 10
|
||||
bb338:
|
||||
ret i32 11
|
||||
bb339:
|
||||
ret i32 12
|
||||
bb340:
|
||||
ret i32 13
|
||||
bb341:
|
||||
ret i32 14
|
||||
bb342:
|
||||
ret i32 15
|
||||
bb343:
|
||||
ret i32 18
|
||||
|
||||
}
|
||||
@ -1,10 +1,10 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep \$5 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep \$7 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep \$6 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep 1024 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep 1023 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep 1024 | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep jg | wc -l | grep 2 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep ja | wc -l | grep 2 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep jg | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep jb | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep jae | wc -l | grep 1 &&
|
||||
; RUN: llvm-as < %s | llc -march=x86 -o - | grep je | wc -l | grep 1
|
||||
|
||||
define i32 @main(i32 %tmp158) {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user