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[X86] Fix missed selection of non-temporal store of zero vector.

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When the input to a store instruction was a zero vector, the backend
always selected a normal vector store regardless of the non-temporal
hint. This is fixed by this patch.

This fixes PR19370.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220054 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio 2014-10-17 17:27:06 +00:00
parent 7023b85187
commit 5512b50db5
2 changed files with 39 additions and 0 deletions
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8
lib/Target/X86/X86InstrSSE.td
View File

@ -3939,6 +3939,14 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
PS, Requires<[HasSSE2]>;
} // SchedRW = [WriteStore]
let Predicates = [HasAVX, NoVLX] in {
def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
(VMOVNTPSmr addr:$dst, VR128:$src)>;
}
def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
(MOVNTPSmr addr:$dst, VR128:$src)>;
} // AddedComplexity
//===----------------------------------------------------------------------===//

31
test/CodeGen/X86/nontemporal-2.ll Normal file
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@ -0,0 +1,31 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
; Make sure that we generate non-temporal stores for the test cases below.
define void @test1(<4 x float>* %dst) {
; CHECK-LABEL: test1:
; SSE: movntps
; AVX: vmovntps
store <4 x float> zeroinitializer, <4 x float>* %dst, align 16, !nontemporal !1
ret void
}
define void @test2(<4 x i32>* %dst) {
; CHECK-LABEL: test2:
; SSE: movntps
; AVX: vmovntps
store <4 x i32> zeroinitializer, <4 x i32>* %dst, align 16, !nontemporal !1
ret void
}
define void @test3(<2 x double>* %dst) {
; CHECK-LABEL: test3:
; SSE: movntps
; AVX: vmovntps
store <2 x double> zeroinitializer, <2 x double>* %dst, align 16, !nontemporal !1
ret void
}
!1 = metadata !{i32 1}