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ARM: treat [N x i32] and [N x i64] as AAPCS composite types
The logic is almost there already, with our special homogeneous aggregate handling. Tweaking it like this allows front-ends to emit AAPCS compliant code without ever having to count registers or add discarded padding arguments. Only arrays of i32 and i64 are needed to model AAPCS rules, but I decided to apply the logic to all integer arrays for more consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230348 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -7463,11 +7463,8 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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}
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if (Args[i].isNest)
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Flags.setNest();
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if (NeedsRegBlock) {
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if (NeedsRegBlock)
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Flags.setInConsecutiveRegs();
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if (Value == NumValues - 1)
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Flags.setInConsecutiveRegsLast();
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}
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Flags.setOrigAlign(OriginalAlignment);
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MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
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@@ -7516,6 +7513,9 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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CLI.Outs.push_back(MyFlags);
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CLI.OutVals.push_back(Parts[j]);
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}
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if (NeedsRegBlock && Value == NumValues - 1)
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CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
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}
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}
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@@ -7731,11 +7731,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
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}
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if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
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Flags.setNest();
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if (NeedsRegBlock) {
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if (NeedsRegBlock)
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Flags.setInConsecutiveRegs();
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if (Value == NumValues - 1)
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Flags.setInConsecutiveRegsLast();
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}
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Flags.setOrigAlign(OriginalAlignment);
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MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
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@@ -7750,6 +7747,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
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MyFlags.Flags.setOrigAlign(1);
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Ins.push_back(MyFlags);
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}
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if (NeedsRegBlock && Value == NumValues - 1)
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Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
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PartBase += VT.getStoreSize();
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}
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}
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