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Detabify and clean up 80 column violations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-13 23:47:11 +00:00
parent f2ddc64c87
commit 55561d1882
3 changed files with 50 additions and 40 deletions
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3
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -89,7 +89,8 @@ static unsigned decodeARMInstruction(uint32_t &insn) {
return ARM::BFI;
}
// Ditto for STRBT, which is a super-instruction for A8.6.199 Encoding A1 & A2.
// Ditto for STRBT, which is a super-instruction for A8.6.199 Encodings
// A1 & A2.
// As a result, the decoder fails to deocode USAT properly.
if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
return ARM::USAT;

4
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2743,8 +2743,8 @@ static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
N3V_VectorShift, B);
}
static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode,
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
N3V_VectorExtract, B);

29
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -969,7 +969,8 @@ static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
// 011xxx
// 100xxx
// 10100x Generate PC-relative address, see ADR on page A8-32
// 10101x Generate SP-relative address, see ADD (SP plus immediate) on page A8-28
// 10101x Generate SP-relative address, see ADD (SP plus immediate) on
// page A8-28
// 1011xx Miscellaneous 16-bit instructions on page A6-11
// 11000x Store multiple registers, see STM / STMIA / STMEA on page A8-374
// 11001x Load multiple registers, see LDM / LDMIA / LDMFD on page A8-110 a
@ -1401,7 +1402,8 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
//
// Two register operands: Rs Rn ModImm
// One register operands (Rs=0b1111 no explicit dest reg): Rn ModImm
// One register operands (Rn=0b1111 no explicit src reg): Rs ModImm - {t2MOVi, t2MVNi}
// One register operands (Rn=0b1111 no explicit src reg): Rs ModImm -
// {t2MOVi, t2MVNi}
//
// ModImm = ThumbExpandImm(i:imm3:imm8)
static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
@ -1835,13 +1837,15 @@ static bool DisassembleThumb2Ldpci(MCInst &MI, unsigned Opcode,
//
// t2LDRi12: Rd Rn (+)imm12
// t2LDRi8: Rd Rn (+/-)imm8 (+ if Inst{9} == 0b1)
// t2LDRs: Rd Rn Rm ConstantShiftSpecifier (see also DisassembleThumb2DPSoReg)
// t2LDRs: Rd Rn Rm ConstantShiftSpecifier (see also
// DisassembleThumb2DPSoReg)
// t2LDR_POST: Rd Rn Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
// t2LDR_PRE: Rd Rn Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
//
// t2STRi12: Rd Rn (+)imm12
// t2STRi8: Rd Rn (+/-)imm8 (+ if Inst{9} == 0b1)
// t2STRs: Rd Rn Rm ConstantShiftSpecifier (see also DisassembleThumb2DPSoReg)
// t2STRs: Rd Rn Rm ConstantShiftSpecifier (see also
// DisassembleThumb2DPSoReg)
// t2STR_POST: Rn Rd Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
// t2STR_PRE: Rn Rd Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
//
@ -2082,23 +2086,27 @@ static bool DisassembleThumb2LongMul(MCInst &MI, unsigned Opcode, uint32_t insn,
//
// Table A6-9 32-bit Thumb instruction encoding
// op1 op2 op Instruction class, see
// --- ------- -- ------------------------------------------------------------
// --- ------- -- -----------------------------------------------------------
// 01 00xx0xx - Load/store multiple on page A6-23
// 00xx1xx - Load/store dual, load/store exclusive, table branch on page A6-24
// 00xx1xx - Load/store dual, load/store exclusive, table branch on
// page A6-24
// 01xxxxx - Data-processing (shifted register) on page A6-31
// 1xxxxxx - Coprocessor instructions on page A6-40
// 10 x0xxxxx 0 Data-processing (modified immediate) on page A6-15
// x1xxxxx 0 Data-processing (plain binary immediate) on page A6-19
// - 1 Branches and miscellaneous control on page A6-20
// 11 000xxx0 - Store single data item on page A6-30
// 001xxx0 - Advanced SIMD element or structure load/store instructions on page A7-27
// 001xxx0 - Advanced SIMD element or structure load/store instructions
// on page A7-27
// 00xx001 - Load byte, memory hints on page A6-28
// 00xx011 - Load halfword, memory hints on page A6-26
// 00xx101 - Load word on page A6-25
// 00xx111 - UNDEFINED
// 010xxxx - Data-processing (register) on page A6-33
// 0110xxx - Multiply, multiply accumulate, and absolute difference on page A6-38
// 0111xxx - Long multiply, long multiply accumulate, and divide on page A6-39
// 0110xxx - Multiply, multiply accumulate, and absolute difference on
// page A6-38
// 0111xxx - Long multiply, long multiply accumulate, and divide on
// page A6-39
// 1xxxxxx - Coprocessor instructions on page A6-40
//
static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
@ -2175,7 +2183,8 @@ static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
}
} else {
// Table A6-9 32-bit Thumb instruction encoding: Load byte|halfword|word
return DisassembleThumb2LdSt(true, MI,Opcode,insn,NumOps,NumOpsAdded, B);
return DisassembleThumb2LdSt(true, MI, Opcode, insn, NumOps,
NumOpsAdded, B);
}
break;
case 1: