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Rename the IMULri* instructions to IMULrri, as they are actually three address

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instructions.  Add forms of these instructions that read from memory


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-17 04:26:43 +00:00
parent 1e3812c1c5
commit 55b5481255
7 changed files with 75 additions and 17 deletions
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4
lib/Target/X86/InstSelectSimple.cpp
View File

@ -1524,10 +1524,10 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
}
if (Class == cShort) {
BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
return;
} else if (Class == cInt) {
BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
return;
}

31
lib/Target/X86/PeepholeOptimizer.cpp
View File

@ -72,7 +72,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
// immediate despite the fact that the operands are 16 or 32 bits. Because
// this can save three bytes of code size (and icache space), we want to
// shrink them if possible.
case X86::IMULri16: case X86::IMULri32:
case X86::IMULrri16: case X86::IMULrri32:
assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
if (MI->getOperand(2).isImmediate()) {
int Val = MI->getOperand(2).getImmedValue();
@ -81,8 +81,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMULri16: Opcode = X86::IMULri16b; break;
case X86::IMULri32: Opcode = X86::IMULri32b; break;
case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
@ -93,6 +93,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
}
return false;
case X86::IMULrmi16: case X86::IMULrmi32:
assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
if (MI->getOperand(5).isImmediate()) {
int Val = MI->getOperand(5).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
unsigned Scale = MI->getOperand(2).getImmedValue();
unsigned R2 = MI->getOperand(3).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
case X86::ADDri16: case X86::ADDri32:
case X86::ADDmi16: case X86::ADDmi32:
case X86::SUBri16: case X86::SUBri32:

2
lib/Target/X86/Printer.cpp
View File

@ -665,7 +665,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// like: add r32, r/m32
//
// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
// for instructions like the IMULri instructions.
// for instructions like the IMULrri instructions.
//
//
assert(MI->getOperand(0).isRegister() &&

2
lib/Target/X86/X86AsmPrinter.cpp
View File

@ -665,7 +665,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// like: add r32, r/m32
//
// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
// for instructions like the IMULri instructions.
// for instructions like the IMULrri instructions.
//
//
assert(MI->getOperand(0).isRegister() &&

4
lib/Target/X86/X86ISelSimple.cpp
View File

@ -1524,10 +1524,10 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
}
if (Class == cShort) {
BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
return;
} else if (Class == cInt) {
BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
return;
}

18
lib/Target/X86/X86InstrInfo.td
View File

@ -299,12 +299,20 @@ def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carr
def IMULrr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
def IMULrr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
def IMULrm16 : I2A16<"imul", 0xAF, MRMSrcMem>, TB, OpSize;
def IMULrm32 : I2A32<"imul", 0xAF, MRMSrcMem>, TB ;
// These are suprisingly enough not two address instructions!
def IMULrri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize; // R16 = R16*I16
def IMULrri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>; // R32 = R32*I32
def IMULrri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >, OpSize; // R16 = R16*I8
def IMULrri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >; // R32 = R32*I8
def IMULrmi16 : X86Inst<"imul", 0x69, MRMSrcMem, Arg16>, OpSize; // R16 = [mem16]*I16
def IMULrmi32 : X86Inst<"imul", 0x69, MRMSrcMem, Arg32>; // R32 = [mem32]*I32
def IMULrmi16b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >, OpSize; // R16 = [mem16]*I8
def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >; // R32 = [mem32]*I8
// These are suprisingly enough not two addres instructions!
def IMULri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize;
def IMULri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>;
def IMULri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>, OpSize;
def IMULri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>;
// Logical operators...

31
lib/Target/X86/X86PeepholeOpt.cpp
View File

@ -72,7 +72,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
// immediate despite the fact that the operands are 16 or 32 bits. Because
// this can save three bytes of code size (and icache space), we want to
// shrink them if possible.
case X86::IMULri16: case X86::IMULri32:
case X86::IMULrri16: case X86::IMULrri32:
assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
if (MI->getOperand(2).isImmediate()) {
int Val = MI->getOperand(2).getImmedValue();
@ -81,8 +81,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMULri16: Opcode = X86::IMULri16b; break;
case X86::IMULri32: Opcode = X86::IMULri32b; break;
case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
@ -93,6 +93,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
}
return false;
case X86::IMULrmi16: case X86::IMULrmi32:
assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
if (MI->getOperand(5).isImmediate()) {
int Val = MI->getOperand(5).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
unsigned Scale = MI->getOperand(2).getImmedValue();
unsigned R2 = MI->getOperand(3).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
case X86::ADDri16: case X86::ADDri32:
case X86::ADDmi16: case X86::ADDmi32:
case X86::SUBri16: case X86::SUBri32: