6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-22 07:24:47 +00:00
Code Issues Projects Releases Wiki Activity

Rename the IMULri* instructions to IMULrri, as they are actually three address

Browse Source 
instructions.  Add forms of these instructions that read from memory


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-02-17 04:26:43 +00:00
parent 1e3812c1c5
commit 55b5481255
7 changed files with 75 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
lib/Target/X86/PeepholeOptimizer.cpp
View File

@@ -72,7 +72,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
// immediate despite the fact that the operands are 16 or 32 bits. Because
// this can save three bytes of code size (and icache space), we want to
// shrink them if possible.
case X86::IMULri16: case X86::IMULri32:
case X86::IMULrri16: case X86::IMULrri32:
assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
if (MI->getOperand(2).isImmediate()) {
int Val = MI->getOperand(2).getImmedValue();
@@ -81,8 +81,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMULri16: Opcode = X86::IMULri16b; break;
case X86::IMULri32: Opcode = X86::IMULri32b; break;
case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
@@ -93,6 +93,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
}
return false;
case X86::IMULrmi16: case X86::IMULrmi32:
assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
if (MI->getOperand(5).isImmediate()) {
int Val = MI->getOperand(5).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
unsigned Scale = MI->getOperand(2).getImmedValue();
unsigned R2 = MI->getOperand(3).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
case X86::ADDri16: case X86::ADDri32:
case X86::ADDmi16: case X86::ADDmi32:
case X86::SUBri16: case X86::SUBri32: