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Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -48,6 +48,11 @@ namespace llvm {
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/// be capable of handling this kind of change.
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///
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void LowerIntrinsicCall(CallInst *CI);
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/// LowerToByteSwap - Replace a call instruction into a call to bswap
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/// intrinsic. Return false if it has determined the call is not a
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/// simple integer bswap.
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static bool LowerToByteSwap(CallInst *CI);
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};
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}
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@ -538,3 +538,27 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
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"Lowering should have eliminated any uses of the intrinsic call!");
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CI->eraseFromParent();
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}
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bool IntrinsicLowering::LowerToByteSwap(CallInst *CI) {
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// Verify this is a simple bswap.
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if (CI->getNumArgOperands() != 1 ||
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CI->getType() != CI->getArgOperand(0)->getType() ||
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!CI->getType()->isIntegerTy())
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return false;
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (!Ty)
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return false;
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// Okay, we can do this xform, do so now.
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const Type *Tys[] = { Ty };
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Module *M = CI->getParent()->getParent()->getParent();
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Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
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Value *Op = CI->getArgOperand(0);
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Op = CallInst::Create(Int, Op, CI->getName(), CI);
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CI->replaceAllUsesWith(Op);
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CI->eraseFromParent();
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return true;
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}
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@ -2071,7 +2071,6 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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if (!ItinData || ItinData->isEmpty())
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return DefTID.mayLoad() ? 3 : 1;
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
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if (DefMO.getReg() == ARM::CPSR) {
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@ -33,6 +33,7 @@
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#include "llvm/Intrinsics.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -43,6 +44,7 @@
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -6092,6 +6094,37 @@ void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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// ARM Inline Assembly Support
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//===----------------------------------------------------------------------===//
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bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
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// Looking for "rev" which is V6+.
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if (!Subtarget->hasV6Ops())
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return false;
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InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
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std::string AsmStr = IA->getAsmString();
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SmallVector<StringRef, 4> AsmPieces;
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SplitString(AsmStr, AsmPieces, ";\n");
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switch (AsmPieces.size()) {
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default: return false;
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case 1:
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AsmStr = AsmPieces[0];
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AsmPieces.clear();
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SplitString(AsmStr, AsmPieces, " \t,");
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// rev $0, $1
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if (AsmPieces.size() == 3 &&
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AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
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IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (Ty && Ty->getBitWidth() == 32)
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return IntrinsicLowering::LowerToByteSwap(CI);
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}
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break;
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}
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return false;
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}
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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ARMTargetLowering::ConstraintType
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@ -257,6 +257,8 @@ namespace llvm {
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unsigned Depth) const;
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virtual bool ExpandInlineAsm(CallInst *CI) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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@ -28,6 +28,7 @@
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -11729,38 +11730,8 @@ bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
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// X86 Inline Assembly Support
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//===----------------------------------------------------------------------===//
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static bool LowerToBSwap(CallInst *CI) {
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// FIXME: this should verify that we are targetting a 486 or better. If not,
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// we will turn this bswap into something that will be lowered to logical ops
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// instead of emitting the bswap asm. For now, we don't support 486 or lower
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// so don't worry about this.
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// Verify this is a simple bswap.
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if (CI->getNumArgOperands() != 1 ||
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CI->getType() != CI->getArgOperand(0)->getType() ||
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!CI->getType()->isIntegerTy())
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return false;
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (!Ty || Ty->getBitWidth() % 16 != 0)
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return false;
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// Okay, we can do this xform, do so now.
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const Type *Tys[] = { Ty };
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Module *M = CI->getParent()->getParent()->getParent();
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Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
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Value *Op = CI->getArgOperand(0);
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Op = CallInst::Create(Int, Op, CI->getName(), CI);
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CI->replaceAllUsesWith(Op);
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CI->eraseFromParent();
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return true;
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}
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bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
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InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
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std::string AsmStr = IA->getAsmString();
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@ -11775,6 +11746,10 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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AsmPieces.clear();
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SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
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// FIXME: this should verify that we are targetting a 486 or better. If not,
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// we will turn this bswap into something that will be lowered to logical ops
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// instead of emitting the bswap asm. For now, we don't support 486 or lower
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// so don't worry about this.
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// bswap $0
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if (AsmPieces.size() == 2 &&
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(AsmPieces[0] == "bswap" ||
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@ -11784,7 +11759,10 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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AsmPieces[1] == "${0:q}")) {
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// No need to check constraints, nothing other than the equivalent of
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// "=r,0" would be valid here.
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return LowerToBSwap(CI);
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (!Ty || Ty->getBitWidth() % 16 != 0)
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return false;
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return IntrinsicLowering::LowerToByteSwap(CI);
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}
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// rorw $$8, ${0:w} --> llvm.bswap.i16
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if (CI->getType()->isIntegerTy(16) &&
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@ -11794,15 +11772,18 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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AsmPieces[2] == "${0:w}" &&
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IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
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AsmPieces.clear();
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const std::string &Constraints = IA->getConstraintString();
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SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
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const std::string &ConstraintsStr = IA->getConstraintString();
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SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
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std::sort(AsmPieces.begin(), AsmPieces.end());
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if (AsmPieces.size() == 4 &&
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AsmPieces[0] == "~{cc}" &&
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AsmPieces[1] == "~{dirflag}" &&
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AsmPieces[2] == "~{flags}" &&
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AsmPieces[3] == "~{fpsr}") {
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return LowerToBSwap(CI);
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (!Ty || Ty->getBitWidth() % 16 != 0)
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return false;
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return IntrinsicLowering::LowerToByteSwap(CI);
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}
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}
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break;
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@ -11822,36 +11803,45 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
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if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
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Words[2] == "${0:w}") {
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AsmPieces.clear();
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const std::string &Constraints = IA->getConstraintString();
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SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
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const std::string &ConstraintsStr = IA->getConstraintString();
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SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
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std::sort(AsmPieces.begin(), AsmPieces.end());
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if (AsmPieces.size() == 4 &&
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AsmPieces[0] == "~{cc}" &&
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AsmPieces[1] == "~{dirflag}" &&
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AsmPieces[2] == "~{flags}" &&
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AsmPieces[3] == "~{fpsr}") {
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return LowerToBSwap(CI);
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (!Ty || Ty->getBitWidth() % 16 != 0)
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return false;
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return IntrinsicLowering::LowerToByteSwap(CI);
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}
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}
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}
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}
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}
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if (CI->getType()->isIntegerTy(64) &&
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Constraints.size() >= 2 &&
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Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
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Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
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// bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
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SmallVector<StringRef, 4> Words;
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SplitString(AsmPieces[0], Words, " \t");
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if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
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Words.clear();
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SplitString(AsmPieces[1], Words, " \t");
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if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
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if (CI->getType()->isIntegerTy(64)) {
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InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
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if (Constraints.size() >= 2 &&
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Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
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Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
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// bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
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SmallVector<StringRef, 4> Words;
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SplitString(AsmPieces[0], Words, " \t");
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if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
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Words.clear();
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SplitString(AsmPieces[2], Words, " \t,");
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if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
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Words[2] == "%edx") {
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return LowerToBSwap(CI);
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SplitString(AsmPieces[1], Words, " \t");
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if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
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Words.clear();
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SplitString(AsmPieces[2], Words, " \t,");
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if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
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Words[2] == "%edx") {
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const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
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if (!Ty || Ty->getBitWidth() % 16 != 0)
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return false;
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return IntrinsicLowering::LowerToByteSwap(CI);
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}
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}
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}
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}
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9
test/CodeGen/ARM/bswap-inline-asm.ll
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9
test/CodeGen/ARM/bswap-inline-asm.ll
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@ -0,0 +1,9 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
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define i32 @t1(i32 %x) nounwind {
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; CHECK: t1:
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; CHECK-NOT: InlineAsm
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; CHECK: rev
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%asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind
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ret i32 %asmtmp
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}
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86-64 > %t
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; RUN: not grep APP %t
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; RUN: llc < %s -mtriple=x86_64-apple-darwin > %t
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; RUN: not grep InlineAsm %t
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; RUN: FileCheck %s < %t
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; CHECK: foo:
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