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Convert LiveRegUnits methods to the current convention (it's new code).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192619 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-10-14 20:45:09 +00:00
parent 655a10d96c
commit 5601abb60d
2 changed files with 27 additions and 27 deletions
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30
include/llvm/CodeGen/LiveRegUnits.h
View File

@ -42,13 +42,13 @@ namespace llvm {
} }
/// Adds a register to the set. /// Adds a register to the set.
void AddReg(unsigned Reg, const MCRegisterInfo &MCRI) { void addReg(unsigned Reg, const MCRegisterInfo &MCRI) {
for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
LiveUnits.insert(*RUnits); LiveUnits.insert(*RUnits);
} }
/// Removes a register from the set. /// Removes a register from the set.
void RemoveReg(unsigned Reg, const MCRegisterInfo &MCRI) { void removeReg(unsigned Reg, const MCRegisterInfo &MCRI) {
for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
LiveUnits.erase(*RUnits); LiveUnits.erase(*RUnits);
} }
@ -57,13 +57,13 @@ namespace llvm {
/// Note that we assume the high bits of a physical super register are not /// Note that we assume the high bits of a physical super register are not
/// preserved unless the instruction has an implicit-use operand reading /// preserved unless the instruction has an implicit-use operand reading
/// the super-register or a register unit for the upper bits is available. /// the super-register or a register unit for the upper bits is available.
void RemoveRegsInMask(const MachineOperand &Op, void removeRegsInMask(const MachineOperand &Op,
const MCRegisterInfo &MCRI) { const MCRegisterInfo &MCRI) {
const uint32_t *Mask = Op.getRegMask(); const uint32_t *Mask = Op.getRegMask();
unsigned Bit = 0; unsigned Bit = 0;
for (unsigned R = 0; R < MCRI.getNumRegs(); ++R) { for (unsigned R = 0; R < MCRI.getNumRegs(); ++R) {
if ((*Mask & (1u << Bit)) == 0) if ((*Mask & (1u << Bit)) == 0)
RemoveReg(R, MCRI); removeReg(R, MCRI);
++Bit; ++Bit;
if (Bit >= 32) { if (Bit >= 32) {
Bit = 0; Bit = 0;
@ -74,7 +74,7 @@ namespace llvm {
/// Returns true if register @p Reg (or one of its super register) is /// Returns true if register @p Reg (or one of its super register) is
/// contained in the set. /// contained in the set.
bool Contains(unsigned Reg, const MCRegisterInfo &MCRI) const { bool contains(unsigned Reg, const MCRegisterInfo &MCRI) const {
for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) { for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) {
if (LiveUnits.count(*RUnits)) if (LiveUnits.count(*RUnits))
return true; return true;
@ -84,7 +84,7 @@ namespace llvm {
/// Simulates liveness when stepping backwards over an instruction(bundle): /// Simulates liveness when stepping backwards over an instruction(bundle):
/// Defs are removed from the set, uses added. /// Defs are removed from the set, uses added.
void StepBackward(const MachineInstr &MI, const MCRegisterInfo &MCRI) { void stepBackward(const MachineInstr &MI, const MCRegisterInfo &MCRI) {
// Remove defined registers and regmask kills from the set. // Remove defined registers and regmask kills from the set.
for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
if (O->isReg()) { if (O->isReg()) {
@ -93,9 +93,9 @@ namespace llvm {
unsigned Reg = O->getReg(); unsigned Reg = O->getReg();
if (Reg == 0) if (Reg == 0)
continue; continue;
RemoveReg(Reg, MCRI); removeReg(Reg, MCRI);
} else if (O->isRegMask()) { } else if (O->isRegMask()) {
RemoveRegsInMask(*O, MCRI); removeRegsInMask(*O, MCRI);
} }
} }
// Add uses to the set. // Add uses to the set.
@ -105,7 +105,7 @@ namespace llvm {
unsigned Reg = O->getReg(); unsigned Reg = O->getReg();
if (Reg == 0) if (Reg == 0)
continue; continue;
AddReg(Reg, MCRI); addReg(Reg, MCRI);
} }
} }
@ -115,7 +115,7 @@ namespace llvm {
/// Uses with kill flag get removed from the set, defs added. If possible /// Uses with kill flag get removed from the set, defs added. If possible
/// use StepBackward() instead of this function because some kill flags may /// use StepBackward() instead of this function because some kill flags may
/// be missing. /// be missing.
void StepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI) { void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI) {
SmallVector<unsigned, 4> Defs; SmallVector<unsigned, 4> Defs;
// Remove killed registers from the set. // Remove killed registers from the set.
for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
@ -130,23 +130,23 @@ namespace llvm {
if (!O->isKill()) if (!O->isKill())
continue; continue;
assert(O->isUse()); assert(O->isUse());
RemoveReg(Reg, MCRI); removeReg(Reg, MCRI);
} }
} else if (O->isRegMask()) { } else if (O->isRegMask()) {
RemoveRegsInMask(*O, MCRI); removeRegsInMask(*O, MCRI);
} }
} }
// Add defs to the set. // Add defs to the set.
for (unsigned i = 0, e = Defs.size(); i != e; ++i) { for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
AddReg(Defs[i], MCRI); addReg(Defs[i], MCRI);
} }
} }
/// Adds all registers in the live-in list of block @p BB. /// Adds all registers in the live-in list of block @p BB.
void AddLiveIns(const MachineBasicBlock &BB, const MCRegisterInfo &MCRI) { void addLiveIns(const MachineBasicBlock &BB, const MCRegisterInfo &MCRI) {
for (MachineBasicBlock::livein_iterator L = BB.livein_begin(), for (MachineBasicBlock::livein_iterator L = BB.livein_begin(),
LE = BB.livein_end(); L != LE; ++L) { LE = BB.livein_end(); L != LE; ++L) {
AddReg(*L, MCRI); addReg(*L, MCRI);
} }
} }
}; };

24
lib/CodeGen/IfConversion.cpp
View File

@ -976,15 +976,15 @@ static void UpdatePredRedefs(MachineInstr *MI, LiveRegUnits &Redefs,
unsigned Reg = Ops->getReg(); unsigned Reg = Ops->getReg();
if (Reg == 0) if (Reg == 0)
continue; continue;
Redefs.RemoveReg(Reg, *TRI); Redefs.removeReg(Reg, *TRI);
} }
for (MIBundleOperands Ops(MI); Ops.isValid(); ++Ops) { for (MIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
if (!Ops->isReg() || !Ops->isDef()) if (!Ops->isReg() || !Ops->isDef())
continue; continue;
unsigned Reg = Ops->getReg(); unsigned Reg = Ops->getReg();
if (Reg == 0 || Redefs.Contains(Reg, *TRI)) if (Reg == 0 || Redefs.contains(Reg, *TRI))
continue; continue;
Redefs.AddReg(Reg, *TRI); Redefs.addReg(Reg, *TRI);
MachineOperand &Op = *Ops; MachineOperand &Op = *Ops;
MachineInstr *MI = Op.getParent(); MachineInstr *MI = Op.getParent();
@ -1001,7 +1001,7 @@ static void RemoveKills(MachineInstr &MI, const LiveRegUnits &DontKill,
for (MIBundleOperands O(&MI); O.isValid(); ++O) { for (MIBundleOperands O(&MI); O.isValid(); ++O) {
if (!O->isReg() || !O->isKill()) if (!O->isReg() || !O->isKill())
continue; continue;
if (DontKill.Contains(O->getReg(), MCRI)) if (DontKill.contains(O->getReg(), MCRI))
O->setIsKill(false); O->setIsKill(false);
} }
} }
@ -1049,13 +1049,13 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
// Initialize liveins to the first BB. These are potentiall redefined by // Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions. // predicated instructions.
LiveRegUnits Redefs; LiveRegUnits Redefs;
Redefs.AddLiveIns(*(CvtBBI->BB), *TRI); Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
Redefs.AddLiveIns(*(NextBBI->BB), *TRI); Redefs.addLiveIns(*(NextBBI->BB), *TRI);
// Compute a set of registers which must not be killed by instructions in // Compute a set of registers which must not be killed by instructions in
// BB1: This is everything live-in to BB2. // BB1: This is everything live-in to BB2.
LiveRegUnits DontKill; LiveRegUnits DontKill;
DontKill.AddLiveIns(*(NextBBI->BB), *TRI); DontKill.addLiveIns(*(NextBBI->BB), *TRI);
if (CvtBBI->BB->pred_size() > 1) { if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
@ -1154,8 +1154,8 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
// Initialize liveins to the first BB. These are potentially redefined by // Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions. // predicated instructions.
LiveRegUnits Redefs; LiveRegUnits Redefs;
Redefs.AddLiveIns(*(CvtBBI->BB), *TRI); Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
Redefs.AddLiveIns(*(NextBBI->BB), *TRI); Redefs.addLiveIns(*(NextBBI->BB), *TRI);
bool HasEarlyExit = CvtBBI->FalseBB != NULL; bool HasEarlyExit = CvtBBI->FalseBB != NULL;
if (CvtBBI->BB->pred_size() > 1) { if (CvtBBI->BB->pred_size() > 1) {
@ -1282,7 +1282,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
// Initialize liveins to the first BB. These are potentially redefined by // Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions. // predicated instructions.
LiveRegUnits Redefs; LiveRegUnits Redefs;
Redefs.AddLiveIns(*(BBI1->BB), *TRI); Redefs.addLiveIns(*(BBI1->BB), *TRI);
// Remove the duplicated instructions at the beginnings of both paths. // Remove the duplicated instructions at the beginnings of both paths.
MachineBasicBlock::iterator DI1 = BBI1->BB->begin(); MachineBasicBlock::iterator DI1 = BBI1->BB->begin();
@ -1315,12 +1315,12 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
LiveRegUnits DontKill; LiveRegUnits DontKill;
for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(), for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(),
E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) { E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
DontKill.StepBackward(*I, *TRI); DontKill.stepBackward(*I, *TRI);
} }
for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E; for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E;
++I) { ++I) {
Redefs.StepForward(*I, *TRI); Redefs.stepForward(*I, *TRI);
} }
BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1); BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
BBI2->BB->erase(BBI2->BB->begin(), DI2); BBI2->BB->erase(BBI2->BB->begin(), DI2);