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AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PD
and VPERMI2W/D/Q/PS/PD. Intrinsics and tests for them are comming in the next patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239999 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
@@ -1058,118 +1058,82 @@ def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
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(VPERMILPDZri VR512:$src1, imm:$imm)>;
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// -- VPERM2I - 3 source operands form --
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multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
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PatFrag mem_frag, X86MemOperand x86memop,
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SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
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multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo _> {
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let Constraints = "$src1 = $dst" in {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
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EVEX_4V;
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defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(_.VT (X86VPermiv3 _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
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AVX5128IBase;
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def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst {${mask}}|"
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"$dst {${mask}}, $src2, $src3}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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RC:$src3),
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RC:$src1)))]>,
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EVEX_4V, EVEX_K;
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let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
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def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst {${mask}} {z} |",
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"$dst {${mask}} {z}, $src2, $src3}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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RC:$src3),
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(OpVT (bitconvert
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(v16i32 immAllZerosV))))))]>,
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EVEX_4V, EVEX_KZ;
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3))))]>, EVEX_4V;
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def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst {${mask}}|"
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"$dst {${mask}}, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3)),
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RC:$src1)))]>,
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EVEX_4V, EVEX_K;
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let AddedComplexity = 10 in // Prefer over the rrkz variant
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def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst {${mask}} {z}|"
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"$dst {${mask}} {z}, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3)),
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(OpVT (bitconvert
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(v16i32 immAllZerosV))))))]>,
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EVEX_4V, EVEX_KZ;
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let mayLoad = 1 in
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defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.MemOp:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(_.VT (X86VPermiv3 _.RC:$src1, _.RC:$src2,
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(_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
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EVEX_4V, AVX5128IBase;
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}
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}
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defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
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i512mem, X86VPermiv3, v16i32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
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i512mem, X86VPermiv3, v8i64, VK8WM>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
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i512mem, X86VPermiv3, v16f32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
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i512mem, X86VPermiv3, v8f64, VK8WM>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
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PatFrag mem_frag, X86MemOperand x86memop,
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SDNode OpNode, ValueType OpVT, RegisterClass KRC,
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ValueType MaskVT, RegisterClass MRC> :
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avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
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OpVT, KRC> {
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def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
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VR512:$idx, VR512:$src1, VR512:$src2, -1)),
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(!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
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def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
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VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
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(!cast<Instruction>(NAME#rrk) VR512:$src1,
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(MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
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multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo _> {
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let mayLoad = 1, Constraints = "$src1 = $dst" in
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defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.ScalarMemOp:$src3),
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OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
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!strconcat("$src2, ${src3}", _.BroadcastStr ),
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(_.VT (X86VPermiv3 _.RC:$src1,
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_.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
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AVX5128IBase, EVEX_4V, EVEX_B;
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}
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defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
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X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
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X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
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X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
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X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo VTInfo> {
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let Predicates = [HasAVX512] in
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defm NAME: avx512_perm_3src<opc, OpcodeStr, VTInfo.info512>,
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avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
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let Predicates = [HasVLX] in {
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defm NAME#128: avx512_perm_3src<opc, OpcodeStr, VTInfo.info128>,
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avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
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defm NAME#256: avx512_perm_3src<opc, OpcodeStr, VTInfo.info256>,
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avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
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}
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}
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multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo VTInfo> {
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let Predicates = [HasBWI] in
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defm NAME: avx512_perm_3src<opc, OpcodeStr, VTInfo.info512>,
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avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
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let Predicates = [HasBWI, HasVLX] in {
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defm NAME#128: avx512_perm_3src<opc, OpcodeStr, VTInfo.info128>,
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avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
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defm NAME#256: avx512_perm_3src<opc, OpcodeStr, VTInfo.info256>,
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avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
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}
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}
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defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", avx512vl_i32_info>,
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EVEX_CD8<32, CD8VF>;
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defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", avx512vl_i64_info>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", avx512vl_f32_info>,
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EVEX_CD8<32, CD8VF>;
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defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", avx512vl_f64_info>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", avx512vl_i32_info>,
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EVEX_CD8<32, CD8VF>;
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defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", avx512vl_i64_info>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", avx512vl_f32_info>,
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EVEX_CD8<32, CD8VF>;
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defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", avx512vl_f64_info>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", avx512vl_i16_info>,
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VEX_W, EVEX_CD8<16, CD8VF>;
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defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", avx512vl_i16_info>,
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VEX_W, EVEX_CD8<16, CD8VF>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - BLEND using mask
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