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Temporarily work around new address lowering while I figure out what

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needs to happen for darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114577 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-09-22 20:42:08 +00:00
parent bfbe187593
commit 56a8b817b1
1 changed files with 2 additions and 1 deletions
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lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -1149,7 +1149,8 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
// that are not a MemSDNode, and thus don't have proper addrspace info.
Parent->getOpcode() != ISD::PREFETCH &&
Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
Parent->getOpcode() != ISD::INTRINSIC_VOID) { // nontemporal stores.
Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
unsigned AddrSpace =
cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
// AddrSpace 256 -> GS, 257 -> FS.