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Fix a typo in a comment.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89360 91177308-0d34-0410-b5e6-96231b3b80d8
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Dan Gohman 2009-11-19 16:35:11 +00:00
parent 90c583fff0
commit 57474fa0f6
1 changed files with 1 additions and 1 deletions
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lib/Target/Blackfin/BlackfinRegisterInfo.td
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@ -44,7 +44,7 @@ class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> {
let Num = num;
}
// Ywo halves of 32-bit register
// Two halves of 32-bit register
multiclass Rss<bits<3> group, bits<3> num, string n> {
def H : Rs<group, num, 1, !strconcat(n, ".h")>;
def L : Rs<group, num, 0, !strconcat(n, ".l")>;