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[ARM64] Add a big endian version of the ARM64 target machine, and update all users.

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This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206965 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy
2014-04-23 10:26:40 +00:00
parent 4231346c8d
commit 57683b8aba
14 changed files with 139 additions and 44 deletions
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35
lib/Target/ARM64/ARM64TargetMachine.cpp
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@@ -49,7 +49,8 @@ EnableDeadRegisterElimination("arm64-dead-def-elimination", cl::Hidden,
extern "C" void LLVMInitializeARM64Target() {
// Register the target.
RegisterTargetMachine<ARM64TargetMachine> X(TheARM64Target);
RegisterTargetMachine<ARM64leTargetMachine> X(TheARM64leTarget);
RegisterTargetMachine<ARM64beTargetMachine> Y(TheARM64beTarget);
}
/// TargetMachine ctor - Create an ARM64 architecture model.
@@ -58,16 +59,40 @@ ARM64TargetMachine::ARM64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
CodeGenOpt::Level OL,
bool LittleEndian)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
DL(Subtarget.isTargetMachO() ? "e-m:o-i64:64-i128:128-n32:64-S128"
: "e-m:e-i64:64-i128:128-n32:64-S128"),
Subtarget(TT, CPU, FS, LittleEndian),
// This nested ternary is horrible, but DL needs to be properly initialized
// before TLInfo is constructed.
DL(Subtarget.isTargetMachO() ?
"e-m:o-i64:64-i128:128-n32:64-S128" :
(LittleEndian ?
"e-m:e-i64:64-i128:128-n32:64-S128" :
"E-m:e-i64:64-i128:128-n32:64-S128")),
InstrInfo(Subtarget), TLInfo(*this), FrameLowering(*this, Subtarget),
TSInfo(*this) {
initAsmInfo();
}
void ARM64leTargetMachine::anchor() { }
ARM64leTargetMachine::
ARM64leTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: ARM64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
void ARM64beTargetMachine::anchor() { }
ARM64beTargetMachine::
ARM64beTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: ARM64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
namespace {
/// ARM64 Code Generator Pass Configuration Options.
class ARM64PassConfig : public TargetPassConfig {