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Fix darwin ppc llvm-gcc build breakage: intercept

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ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG.  This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes.  Probably PPC should
simply custom lower the original conversion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58329 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-10-28 15:00:32 +00:00
parent 42d4499a16
commit 57760d96e2
3 changed files with 75 additions and 5 deletions
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35
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -902,6 +902,18 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
MVT RVT = N->getValueType(0);
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
if (RVT == MVT::i32) {
assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
N->getOperand(0), DAG.getValueType(MVT::f64));
Res = DAG.getNode(ISD::FP_ROUND, MVT::f64, Res, DAG.getIntPtrConstant(1));
return DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Res);
}
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
return MakeLibCall(LC, RVT, &N->getOperand(0), 1, false);
@ -909,6 +921,29 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
MVT RVT = N->getValueType(0);
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
if (RVT == MVT::i32) {
assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat APF = APFloat(APInt(128, 2, TwoE31));
SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
return DAG.getNode(ISD::SELECT_CC, MVT::i32, N->getOperand(0), Tmp,
DAG.getNode(ISD::ADD, MVT::i32,
DAG.getNode(ISD::FP_TO_SINT, MVT::i32,
DAG.getNode(ISD::FSUB,
MVT::ppcf128,
N->getOperand(0),
Tmp)),
DAG.getConstant(0x80000000, MVT::i32)),
DAG.getNode(ISD::FP_TO_SINT, MVT::i32, N->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false);

12
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -2865,9 +2865,10 @@ SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op,
assert(Op.getValueType() == MVT::ppcf128);
SDNode *Node = Op.getNode();
assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
assert(Node->getOperand(0).getNode()->getOpcode() == ISD::BUILD_PAIR);
SDValue Lo = Node->getOperand(0).getNode()->getOperand(0);
SDValue Hi = Node->getOperand(0).getNode()->getOperand(1);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, Node->getOperand(0),
DAG.getIntPtrConstant(0));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, Node->getOperand(0),
DAG.getIntPtrConstant(1));
// This sequence changes FPSCR to do round-to-zero, adds the two halves
// of the long double, and puts FPSCR back the way it was. We do not
@ -2916,7 +2917,7 @@ SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op,
// We know the low half is about to be thrown away, so just use something
// convenient.
return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
return DAG.getNode(ISD::BUILD_PAIR, MVT::ppcf128, FPreg, FPreg);
}
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
@ -3883,7 +3884,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
switch (N->getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
default:
return PPCTargetLowering::LowerOperation(SDValue (N, 0), DAG).getNode();
case ISD::FP_TO_SINT: {
SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG);
// Use MERGE_VALUES to drop the chain result value and get a node with one

33
test/CodeGen/PowerPC/2008-10-28-f128-i32.ll Normal file
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@ -0,0 +1,33 @@
; RUN: llvm-as < %s | llc -march=ppc32 -o - | not grep fixunstfsi
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
entry:
%0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb1
bb1: ; preds = %entry
%1 = mul ppc_fp128 %a, 0xM3DF00000000000000000000000000000 ; <ppc_fp128> [#uses=1]
%2 = fptoui ppc_fp128 %1 to i32 ; <i32> [#uses=1]
%3 = zext i32 %2 to i64 ; <i64> [#uses=1]
%4 = shl i64 %3, 32 ; <i64> [#uses=3]
%5 = uitofp i64 %4 to ppc_fp128 ; <ppc_fp128> [#uses=1]
%6 = sub ppc_fp128 %a, %5 ; <ppc_fp128> [#uses=3]
%7 = fcmp olt ppc_fp128 %6, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
br i1 %7, label %bb2, label %bb3
bb2: ; preds = %bb1
%8 = sub ppc_fp128 0xM80000000000000000000000000000000, %6 ; <ppc_fp128> [#uses=1]
%9 = fptoui ppc_fp128 %8 to i32 ; <i32> [#uses=1]
%10 = zext i32 %9 to i64 ; <i64> [#uses=1]
%11 = sub i64 %4, %10 ; <i64> [#uses=1]
ret i64 %11
bb3: ; preds = %bb1
%12 = fptoui ppc_fp128 %6 to i32 ; <i32> [#uses=1]
%13 = zext i32 %12 to i64 ; <i64> [#uses=1]
%14 = or i64 %13, %4 ; <i64> [#uses=1]
ret i64 %14
bb5: ; preds = %entry
ret i64 0
}