implement uncond branch insertion, mark branches with isBranch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31160 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

@@ -48,3 +48,11 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
   }
   return false;
 }
+
+void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+                                  MachineBasicBlock *FBB,
+                                  const std::vector<MachineOperand> &Cond)const{
+  // Can only insert uncond branches so far.
+  assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
+  BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+}

lib/Target/ARM/ARMInstrInfo.h

@@ -40,6 +40,10 @@ public:
   ///
   virtual bool isMoveInstr(const MachineInstr &MI,
                            unsigned &SrcReg, unsigned &DstReg) const;
+
+  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                            MachineBasicBlock *FBB,
+                            const std::vector<MachineOperand> &Cond) const;
 };
 
 }

lib/Target/ARM/ARMInstrInfo.td

@@ -227,7 +227,7 @@ let Defs = [R0] in {
   def UMULL   : IntBinOp<"umull r12,", mulhu>;
 }
 
-let isTerminator = 1 in {
+let isTerminator = 1, isBranch = 1 in {
   def bcond   : InstARM<(ops brtarget:$dst, CCOp:$cc),
 	                    "b$cc $dst",
 		            [(armbr bb:$dst, imm:$cc)]>;