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[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132
This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226573 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kai Nacke
parent
c7fa62b126
commit
57e80129b9
@ -16,6 +16,10 @@
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//===----------------------------------------------------------------------===//
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// Unsigned Operand
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def uimm5_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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@ -41,6 +45,38 @@ def immSExt10_64 : PatLeaf<(i64 imm),
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def immZExt16_64 : PatLeaf<(i64 imm),
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[{ return isInt<16>(N->getZExtValue()); }]>;
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def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
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// Transformation function: get log2 of low 32 bits of immediate
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def Log2LO : SDNodeXForm<imm, [{
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return getImm(N, Log2_64((unsigned) N->getZExtValue()));
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}]>;
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// Transformation function: get log2 of high 32 bits of immediate
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def Log2HI : SDNodeXForm<imm, [{
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return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
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}]>;
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// Predicate: True if immediate is a power of 2 and fits 32 bits
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def PowerOf2LO : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i64) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
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}
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else
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return false;
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}]>;
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// Predicate: True if immediate is a power of 2 and exceeds 32 bits
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def PowerOf2HI : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i64) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
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}
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else
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return false;
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}]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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@ -305,12 +341,34 @@ class SetCC64_I<string opstr, PatFrag cond_op>:
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let TwoOperandAliasConstraint = "$rt = $rs";
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}
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class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
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RegisterOperand RO, bits<64> shift = 1> :
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InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset),
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!strconcat(opstr, "\t$rs, $p, $offset"),
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[(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
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bb:$offset)], IIBranch, FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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}
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// Unsigned Byte Add
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let Pattern = [(set GPR64Opnd:$rd,
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(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
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def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
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ADD_FM<0x1c, 0x28>;
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// Branch on Bit Clear /+32
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def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>;
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def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>,
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BBIT_FM<0x36>;
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// Branch on Bit Set /+32
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def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>;
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def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>,
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BBIT_FM<0x3e>;
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// Multiply Doubleword to GPR
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let Defs = [HI0, LO0, P0, P1, P2] in
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def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
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@ -440,6 +498,18 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
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// bswap MipsPattern
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def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
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// Octeon bbit0/bbit1 MipsPattern
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let Predicates = [HasMips64, HasCnMips] in {
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def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
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(BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
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def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
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(BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
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def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
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(BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
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def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
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(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
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}
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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@ -297,6 +297,19 @@ class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
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let Inst{15-0} = offset;
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}
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class BBIT_FM<bits<6> op> : StdArch {
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bits<5> rs;
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bits<5> p;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = p;
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let Inst{15-0} = offset;
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}
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class SLTI_FM<bits<6> op> : StdArch {
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bits<5> rt;
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bits<5> rs;
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@ -93,3 +93,75 @@ entry:
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%res2 = zext i1 %res to i64
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ret i64 %res2
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}
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define i64 @bbit0(i64 %a) nounwind {
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entry:
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; OCTEON-LABEL: bbit0:
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; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64-LABEL: bbit0:
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; MIPS64: andi $[[T0:[0-9]+]], $4, 8
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; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 8
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%res = icmp eq i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit032(i64 %a) nounwind {
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entry:
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; OCTEON-LABEL: bbit032:
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; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64-LABEL: bbit032:
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; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
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; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
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; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
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; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 34359738368
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%res = icmp eq i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit1(i64 %a) nounwind {
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entry:
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; OCTEON-LABEL: bbit1:
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; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64-LABEL: bbit1:
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; MIPS64: andi $[[T0:[0-9]+]], $4, 8
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; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 8
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%res = icmp ne i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit132(i64 %a) nounwind {
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entry:
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; OCTEON-LABEL: bbit132:
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; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64-LABEL: bbit132:
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; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
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; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
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; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
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; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 34359738368
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%res = icmp ne i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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@ -3,6 +3,10 @@
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# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
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# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
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# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28]
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# CHECK: bbit0 $19, 22, foo # encoding: [0xca,0x76,A,A]
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# CHECK: bbit032 $fp, 11, foo # encoding: [0xdb,0xcb,A,A]
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# CHECK: bbit1 $3, 31, foo # encoding: [0xe8,0x7f,A,A]
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# CHECK: bbit132 $24, 10, foo # encoding: [0xfb,0x0a,A,A]
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# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2]
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# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72]
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# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3]
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@ -46,9 +50,14 @@
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# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f]
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# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f]
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foo:
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baddu $9, $6, $7
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baddu $17, $18, $19
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baddu $2, $3
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bbit0 $19, 22, foo
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bbit032 $30, 11, foo
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bbit1 $3, 31, foo
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bbit132 $24, 10, foo
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cins $25, $10, 22, 2
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cins $9, 17, 29
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cins32 $15, $2, 18, 8
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