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Remove dead code. Fix associated test to use FileCheck.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
2011-05-16 21:28:22 +00:00
parent 227dfdb3c4
commit 57f4b03621
2 changed files with 14 additions and 15 deletions
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14
lib/Target/X86/X86ISelLowering.cpp
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@@ -1527,20 +1527,6 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
// This truncation won't change the value. // This truncation won't change the value.
DAG.getIntPtrConstant(1)); DAG.getIntPtrConstant(1));
} else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
// For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
MVT::v2i64, InFlag).getValue(1);
Val = Chain.getValue(0);
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
Val, DAG.getConstant(0, MVT::i64));
} else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
MVT::i64, InFlag).getValue(1);
Val = Chain.getValue(0);
}
Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
} else { } else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
CopyVT, InFlag).getValue(1); CopyVT, InFlag).getValue(1);

15
test/CodeGen/X86/ret-mmx.ll
View File

@@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mattr=+mmx,+sse2 | FileCheck %s
; rdar://6602459 ; rdar://6602459
@g_v1di = external global <1 x i64> @g_v1di = external global <1 x i64>
@@ -8,19 +8,32 @@ entry:
%call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0] %call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
store <1 x i64> %call, <1 x i64>* @g_v1di store <1 x i64> %call, <1 x i64>* @g_v1di
ret void ret void
; CHECK: t1:
; CHECK: callq
; CHECK-NEXT: movq _g_v1di
; CHECK-NEXT: movq %rax,
} }
declare <1 x i64> @return_v1di() declare <1 x i64> @return_v1di()
define <1 x i64> @t2() nounwind { define <1 x i64> @t2() nounwind {
ret <1 x i64> <i64 1> ret <1 x i64> <i64 1>
; CHECK: t2:
; CHECK: movl $1
; CHECK-NEXT: ret
} }
define <2 x i32> @t3() nounwind { define <2 x i32> @t3() nounwind {
ret <2 x i32> <i32 1, i32 0> ret <2 x i32> <i32 1, i32 0>
; CHECK: t3:
; CHECK: movl $1
; CHECK: movd {{.*}}, %xmm0
} }
define double @t4() nounwind { define double @t4() nounwind {
ret double bitcast (<2 x i32> <i32 1, i32 0> to double) ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
; CHECK: t4:
; CHECK: movl $1
; CHECK: movd {{.*}}, %xmm0
} }