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Define new-value store instructions with base+immediate addressing mode
using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169432 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
46defa599b
commit
5807fd41a7
@ -2372,6 +2372,59 @@ def : Pat<(store (i32 IntRegs:$src1),
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// NV/ST +
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//===----------------------------------------------------------------------===//
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// multiclass for new-value store instructions with base + immediate offset.
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//
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multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
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Operand predImmOp, bit isNot, bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME#_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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}
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multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
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bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
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}
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}
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let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
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multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
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Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
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bits<5> PredImmBits> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
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let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
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isPredicable = 1 in
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def #NAME#_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
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#mnemonic#"($src1+#$src2) = $src3.new",
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[]>,
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Requires<[HasV4T]>;
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let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
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isPredicated = 1 in {
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defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
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defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
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}
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}
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}
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let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
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defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 11, 6>, AddrModeRel;
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defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 12, 7>, AddrModeRel;
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defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 13, 8>, AddrModeRel;
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}
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// Store new-value byte.
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// memb(Re=#U6)=Nt.new
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@ -2382,12 +2435,6 @@ def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
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[]>,
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Requires<[HasV4T]>;
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let mayStore = 1, isPredicable = 1 in
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def STrib_indexed_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
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"memb($src1+#$src2) = $src3.new",
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[]>,
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Requires<[HasV4T]>;
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// memb(Ru<<#u2+#U6)=Nt.new
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let mayStore = 1, AddedComplexity = 10 in
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def STrib_shl_nv_V4 : NVInst_V4<(outs),
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@ -2464,42 +2511,6 @@ def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) memb(Rs+#u6:0)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
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"if ($src1) memb($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) memb(Rs+#u6:0)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
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"if ($src1.new) memb($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memb(Rs+#u6:0)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
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"if (!$src1) memb($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) memb(Rs+#u6:0)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
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"if (!$src1.new) memb($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
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// if (Pv) memb(Rx++#s4:0)=Nt.new
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let mayStore = 1, hasCtrlDep = 1,
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@ -2547,13 +2558,6 @@ def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
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[]>,
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Requires<[HasV4T]>;
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let mayStore = 1, isPredicable = 1 in
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def STrih_indexed_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
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"memh($src1+#$src2) = $src3.new",
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[]>,
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Requires<[HasV4T]>;
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// memh(Ru<<#u2+#U6)=Nt.new
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let mayStore = 1, AddedComplexity = 10 in
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def STrih_shl_nv_V4 : NVInst_V4<(outs),
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@ -2634,42 +2638,6 @@ def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) memh(Rs+#u6:1)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
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"if ($src1) memh($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) memh(Rs+#u6:1)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
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"if ($src1.new) memh($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memh(Rs+#u6:1)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
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"if (!$src1) memh($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) memh(Rs+#u6:1)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
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"if (!$src1.new) memh($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
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// if (Pv) memh(Rx++#s4:1)=Nt.new
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let mayStore = 1, hasCtrlDep = 1,
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@ -2719,13 +2687,6 @@ def STriw_nv_V4 : NVInst_V4<(outs),
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[]>,
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Requires<[HasV4T]>;
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let mayStore = 1, isPredicable = 1 in
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def STriw_indexed_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
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"memw($src1+#$src2) = $src3.new",
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[]>,
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Requires<[HasV4T]>;
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// memw(Ru<<#u2+#U6)=Nt.new
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let mayStore = 1, AddedComplexity = 10 in
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def STriw_shl_nv_V4 : NVInst_V4<(outs),
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@ -2803,42 +2764,6 @@ def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
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[]>,
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Requires<[HasV4T]>;
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// if (Pv) memw(Rs+#u6:2)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
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"if ($src1) memw($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) memw(Rs+#u6:2)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
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"if ($src1.new) memw($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memw(Rs+#u6:2)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
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"if (!$src1) memw($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) memw(Rs+#u6:2)=Nt.new
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let mayStore = 1, neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
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"if (!$src1.new) memw($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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// if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
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// if (Pv) memw(Rx++#s4:2)=Nt.new
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let mayStore = 1, hasCtrlDep = 1,
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