mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-05 01:31:05 +00:00
Rewrite pre-increment store patterns to use standard memory operands.
Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
parent
ec8d1a5b72
commit
5882e3d828
@ -814,78 +814,6 @@ def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
"stdx $rS, $dst", LdStSTD,
|
||||
[(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
}
|
||||
|
||||
let PPC970_Unit = 2 in {
|
||||
|
||||
def STBU8 : DForm_1a<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU8 : DForm_1a<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
|
||||
def STWU8 : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
|
||||
def STDU : DSForm_1a<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
|
||||
s16immX4:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stdu $rS, $ptroff($ptrreg)", LdStSTDU,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
isPPC64;
|
||||
|
||||
|
||||
def STBUX8 : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti8 G8RC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STHUX8 : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti16 G8RC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STWUX8 : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti32 G8RC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stdux $rS, $ptroff, $ptrreg", LdStSTDU,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked, isPPC64;
|
||||
|
||||
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
|
||||
def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
|
||||
"std $rT, $dst", LdStSTD,
|
||||
@ -896,6 +824,60 @@ def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
|
||||
PPC970_DGroup_Cracked;
|
||||
}
|
||||
|
||||
// Stores with Update (pre-inc).
|
||||
let PPC970_Unit = 2, mayStore = 1 in {
|
||||
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
|
||||
"stbu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
|
||||
"sthu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
|
||||
"stwu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
|
||||
"stdu $rS, $dst", LdStSTDU, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
|
||||
isPPC64;
|
||||
|
||||
def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
"stbux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
"sthux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
"stwux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
"stdux $rS, $dst", LdStSTDU, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked, isPPC64;
|
||||
}
|
||||
|
||||
// Patterns to match the pre-inc stores. We can't put the patterns on
|
||||
// the instruction definitions directly as ISel wants the address base
|
||||
// and offset to be separate operands, not a single complex operand.
|
||||
def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STBU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STHU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STWU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
|
||||
def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STBUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STHUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STWUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STDUX G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -346,9 +346,6 @@ def s16imm : Operand<i32> {
|
||||
def u16imm : Operand<i32> {
|
||||
let PrintMethod = "printU16ImmOperand";
|
||||
}
|
||||
def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
|
||||
let PrintMethod = "printS16X4ImmOperand";
|
||||
}
|
||||
def directbrtarget : Operand<OtherVT> {
|
||||
let PrintMethod = "printBranchOperand";
|
||||
let EncoderMethod = "getDirectBrEncoding";
|
||||
@ -870,44 +867,39 @@ def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
|
||||
}
|
||||
|
||||
// Unindexed (r+i) Stores with Update (preinc).
|
||||
let PPC970_Unit = 2 in {
|
||||
def STBU : DForm_1a<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU : DForm_1a<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STWU : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res, (pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STFSU : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stfsu $rS, $ptroff($ptrreg)", LdStSTFDU,
|
||||
[(set ptr_rc_nor0:$ea_res, (pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STFDU : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
|
||||
"stfdu $rS, $ptroff($ptrreg)", LdStSTFDU,
|
||||
[(set ptr_rc_nor0:$ea_res, (pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
let PPC970_Unit = 2, mayStore = 1 in {
|
||||
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
|
||||
"stbu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
|
||||
"sthu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
|
||||
"stwu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
|
||||
"stfsu $rS, $dst", LdStSTFDU, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
|
||||
"stfdu $rS, $dst", LdStSTFDU, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
}
|
||||
|
||||
// Patterns to match the pre-inc stores. We can't put the patterns on
|
||||
// the instruction definitions directly as ISel wants the address base
|
||||
// and offset to be separate operands, not a single complex operand.
|
||||
def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STBU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STHU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STFSU F4RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
def : Pat<(pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
|
||||
(STFDU F8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
|
||||
|
||||
// Indexed (r+r) Stores.
|
||||
//
|
||||
let PPC970_Unit = 2 in {
|
||||
def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
"stbx $rS, $dst", LdStStore,
|
||||
@ -922,48 +914,6 @@ def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
[(store GPRC:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins GPRC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti8 GPRC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins GPRC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_truncsti16 GPRC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins GPRC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STFSUX : XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins F4RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stfsux $rS, $ptroff, $ptrreg", LdStSTFDU,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STFDUX : XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res),
|
||||
(ins F8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg),
|
||||
"stfdux $rS, $ptroff, $ptrreg", LdStSTFDU,
|
||||
[(set ptr_rc_nor0:$ea_res,
|
||||
(pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
"sthbrx $rS, $dst", LdStStore,
|
||||
[(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
|
||||
@ -985,6 +935,44 @@ def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
|
||||
[(store F8RC:$frS, xaddr:$dst)]>;
|
||||
}
|
||||
|
||||
// Indexed (r+r) Stores with Update (preinc).
|
||||
let PPC970_Unit = 2, mayStore = 1 in {
|
||||
def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
|
||||
"stbux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
|
||||
"sthux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
|
||||
"stwux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
|
||||
"stfsux $rS, $dst", LdStSTFDU, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
|
||||
"stfdux $rS, $dst", LdStSTFDU, []>,
|
||||
RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
}
|
||||
|
||||
// Patterns to match the pre-inc stores. We can't put the patterns on
|
||||
// the instruction definitions directly as ISel wants the address base
|
||||
// and offset to be separate operands, not a single complex operand.
|
||||
def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STBUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STHUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STWUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STFSUX F4RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
def : Pat<(pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
|
||||
(STFDUX F8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
|
||||
|
||||
def SYNC : XForm_24_sync<31, 598, (outs), (ins),
|
||||
"sync", LdStSync,
|
||||
[(int_ppc_sync)]>;
|
||||
|
||||
170
test/CodeGen/PowerPC/store-update.ll
Normal file
170
test/CodeGen/PowerPC/store-update.ll
Normal file
@ -0,0 +1,170 @@
|
||||
; RUN: llc < %s | FileCheck %s
|
||||
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
||||
target triple = "powerpc64-unknown-linux-gnu"
|
||||
|
||||
define i8* @stbu(i8* %base, i8 zeroext %val) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i8* %base, i64 16
|
||||
store i8 %val, i8* %arrayidx, align 1
|
||||
ret i8* %arrayidx
|
||||
}
|
||||
; CHECK: @stbu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stbu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i8* @stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i8* %base, i64 %offset
|
||||
store i8 %val, i8* %arrayidx, align 1
|
||||
ret i8* %arrayidx
|
||||
}
|
||||
; CHECK: @stbux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stbux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i16* @sthu(i16* %base, i16 zeroext %val) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i16* %base, i64 16
|
||||
store i16 %val, i16* %arrayidx, align 2
|
||||
ret i16* %arrayidx
|
||||
}
|
||||
; CHECK: @sthu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sthu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i16* @sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i16* %base, i64 %offset
|
||||
store i16 %val, i16* %arrayidx, align 2
|
||||
ret i16* %arrayidx
|
||||
}
|
||||
; CHECK: @sthux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sldi
|
||||
; CHECK-NEXT: sthux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i32* @stwu(i32* %base, i32 zeroext %val) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i32* %base, i64 16
|
||||
store i32 %val, i32* %arrayidx, align 4
|
||||
ret i32* %arrayidx
|
||||
}
|
||||
; CHECK: @stwu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stwu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i32* @stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i32* %base, i64 %offset
|
||||
store i32 %val, i32* %arrayidx, align 4
|
||||
ret i32* %arrayidx
|
||||
}
|
||||
; CHECK: @stwux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sldi
|
||||
; CHECK-NEXT: stwux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i8* @stbu8(i8* %base, i64 %val) nounwind {
|
||||
entry:
|
||||
%conv = trunc i64 %val to i8
|
||||
%arrayidx = getelementptr inbounds i8* %base, i64 16
|
||||
store i8 %conv, i8* %arrayidx, align 1
|
||||
ret i8* %arrayidx
|
||||
}
|
||||
; CHECK: @stbu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stbu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i8* @stbux8(i8* %base, i64 %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%conv = trunc i64 %val to i8
|
||||
%arrayidx = getelementptr inbounds i8* %base, i64 %offset
|
||||
store i8 %conv, i8* %arrayidx, align 1
|
||||
ret i8* %arrayidx
|
||||
}
|
||||
; CHECK: @stbux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stbux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i16* @sthu8(i16* %base, i64 %val) nounwind {
|
||||
entry:
|
||||
%conv = trunc i64 %val to i16
|
||||
%arrayidx = getelementptr inbounds i16* %base, i64 16
|
||||
store i16 %conv, i16* %arrayidx, align 2
|
||||
ret i16* %arrayidx
|
||||
}
|
||||
; CHECK: @sthu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sthu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i16* @sthux8(i16* %base, i64 %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%conv = trunc i64 %val to i16
|
||||
%arrayidx = getelementptr inbounds i16* %base, i64 %offset
|
||||
store i16 %conv, i16* %arrayidx, align 2
|
||||
ret i16* %arrayidx
|
||||
}
|
||||
; CHECK: @sthux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sldi
|
||||
; CHECK-NEXT: sthux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i32* @stwu8(i32* %base, i64 %val) nounwind {
|
||||
entry:
|
||||
%conv = trunc i64 %val to i32
|
||||
%arrayidx = getelementptr inbounds i32* %base, i64 16
|
||||
store i32 %conv, i32* %arrayidx, align 4
|
||||
ret i32* %arrayidx
|
||||
}
|
||||
; CHECK: @stwu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stwu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i32* @stwux8(i32* %base, i64 %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%conv = trunc i64 %val to i32
|
||||
%arrayidx = getelementptr inbounds i32* %base, i64 %offset
|
||||
store i32 %conv, i32* %arrayidx, align 4
|
||||
ret i32* %arrayidx
|
||||
}
|
||||
; CHECK: @stwux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sldi
|
||||
; CHECK-NEXT: stwux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i64* @stdu(i64* %base, i64 %val) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i64* %base, i64 16
|
||||
store i64 %val, i64* %arrayidx, align 8
|
||||
ret i64* %arrayidx
|
||||
}
|
||||
; CHECK: @stdu
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: stdu
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
define i64* @stdux(i64* %base, i64 %val, i64 %offset) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds i64* %base, i64 %offset
|
||||
store i64 %val, i64* %arrayidx, align 8
|
||||
ret i64* %arrayidx
|
||||
}
|
||||
; CHECK: @stdux
|
||||
; CHECK: %entry
|
||||
; CHECK-NEXT: sldi
|
||||
; CHECK-NEXT: stdux
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user