mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-01 00:33:09 +00:00
Implement: Jello/test-constantexpr.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
dc3602bf0d
commit
58c41fe687
@ -153,7 +153,9 @@ namespace {
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// Comparison operators...
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void visitSetCondInst(SetCondInst &I);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI);
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// Memory Instructions
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MachineInstr *doFPLoad(MachineBasicBlock *MBB,
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@ -205,6 +207,14 @@ namespace {
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned TargetReg);
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/// emitSetCCOperation - Common code shared between visitSetCondInst and
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/// constant expression support.
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void emitSetCCOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg);
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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@ -337,6 +347,16 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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Class, R);
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return;
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case Instruction::SetNE:
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case Instruction::SetEQ:
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case Instruction::SetLT:
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case Instruction::SetGT:
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case Instruction::SetLE:
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case Instruction::SetGE:
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emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode(), R);
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return;
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expressions not yet handled!\n");
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@ -571,13 +591,14 @@ static const unsigned SetCCOpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
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};
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = Op0->getType();
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bool isSigned = CompTy->isSigned();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = getReg(Op0);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// Special case handling of: cmp R, i
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if (Class == cByte || Class == cShort || Class == cInt)
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@ -588,34 +609,34 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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Op1v &= (1ULL << (8 << Class)) - 1;
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switch (Class) {
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case cByte: BuildMI(BB, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
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case cShort: BuildMI(BB, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
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case cInt: BuildMI(BB, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
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case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
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case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
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case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
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default:
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assert(0 && "Invalid class!");
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}
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return isSigned;
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}
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unsigned Op1r = getReg(Op1);
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unsigned Op1r = getReg(Op1, MBB, IP);
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switch (Class) {
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default: assert(0 && "Unknown type class!");
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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case cByte:
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BuildMI(BB, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
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break;
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case cShort:
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BuildMI(BB, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
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break;
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case cInt:
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BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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break;
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case cFP:
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BuildMI(BB, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, X86::FNSTSWr8, 0);
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BuildMI(BB, X86::SAHF, 1);
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BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::FNSTSWr8, 0);
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BMI(MBB, IP, X86::SAHF, 1);
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isSigned = false; // Compare with unsigned operators
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break;
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@ -624,9 +645,9 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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unsigned LoTmp = makeAnotherReg(Type::IntTy);
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unsigned HiTmp = makeAnotherReg(Type::IntTy);
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unsigned FinalTmp = makeAnotherReg(Type::IntTy);
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BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
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BuildMI(BB, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
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BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
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BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
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break; // Allow the sete or setne to be generated from flags set by OR
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} else {
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// Emit a sequence of code which compares the high and low parts once
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@ -642,13 +663,13 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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// classes! Until then, hardcode registers so that we can deal with their
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// aliases (because we don't have conditional byte moves).
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//
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BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::BH);
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BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::AH);
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BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
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BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
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BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
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BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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// NOTE: visitSetCondInst knows that the value is dumped into the BL
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// register at this point for long values...
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return isSigned;
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@ -664,21 +685,34 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
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unsigned OpNum = getSetCCNumber(I.getOpcode());
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unsigned DestReg = getReg(I);
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bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
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I.getOperand(1));
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MachineBasicBlock::iterator MII = BB->end();
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emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
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DestReg);
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}
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if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
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/// emitSetCCOperation - Common code shared between visitSetCondInst and
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/// constant expression support.
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void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg) {
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unsigned OpNum = getSetCCNumber(Opcode);
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bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP);
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if (getClassB(Op0->getType()) != cLong || OpNum < 2) {
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// Handle normal comparisons with a setcc instruction...
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
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BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
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} else {
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// Handle long comparisons by copying the value which is already in BL into
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// the register we want...
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BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
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BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
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}
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}
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/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
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/// operand, in the specified target register.
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void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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@ -797,8 +831,9 @@ void ISel::visitBranchInst(BranchInst &BI) {
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}
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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MachineBasicBlock::iterator MII = BB->end();
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bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
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SCI->getOperand(1));
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SCI->getOperand(1), BB, MII);
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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@ -153,7 +153,9 @@ namespace {
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// Comparison operators...
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void visitSetCondInst(SetCondInst &I);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI);
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// Memory Instructions
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MachineInstr *doFPLoad(MachineBasicBlock *MBB,
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@ -205,6 +207,14 @@ namespace {
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned TargetReg);
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/// emitSetCCOperation - Common code shared between visitSetCondInst and
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/// constant expression support.
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void emitSetCCOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg);
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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@ -337,6 +347,16 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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Class, R);
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return;
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case Instruction::SetNE:
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case Instruction::SetEQ:
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case Instruction::SetLT:
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case Instruction::SetGT:
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case Instruction::SetLE:
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case Instruction::SetGE:
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emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode(), R);
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return;
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expressions not yet handled!\n");
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@ -571,13 +591,14 @@ static const unsigned SetCCOpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
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};
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = Op0->getType();
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bool isSigned = CompTy->isSigned();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = getReg(Op0);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// Special case handling of: cmp R, i
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if (Class == cByte || Class == cShort || Class == cInt)
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@ -588,34 +609,34 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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Op1v &= (1ULL << (8 << Class)) - 1;
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switch (Class) {
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case cByte: BuildMI(BB, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
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case cShort: BuildMI(BB, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
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case cInt: BuildMI(BB, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
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case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
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case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
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case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
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default:
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assert(0 && "Invalid class!");
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}
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return isSigned;
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}
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unsigned Op1r = getReg(Op1);
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unsigned Op1r = getReg(Op1, MBB, IP);
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switch (Class) {
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default: assert(0 && "Unknown type class!");
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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case cByte:
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BuildMI(BB, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
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break;
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case cShort:
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BuildMI(BB, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
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break;
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case cInt:
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BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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break;
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case cFP:
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BuildMI(BB, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, X86::FNSTSWr8, 0);
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BuildMI(BB, X86::SAHF, 1);
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BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::FNSTSWr8, 0);
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BMI(MBB, IP, X86::SAHF, 1);
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isSigned = false; // Compare with unsigned operators
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break;
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@ -624,9 +645,9 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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unsigned LoTmp = makeAnotherReg(Type::IntTy);
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unsigned HiTmp = makeAnotherReg(Type::IntTy);
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unsigned FinalTmp = makeAnotherReg(Type::IntTy);
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BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
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BuildMI(BB, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
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BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
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BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
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break; // Allow the sete or setne to be generated from flags set by OR
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} else {
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// Emit a sequence of code which compares the high and low parts once
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@ -642,13 +663,13 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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// classes! Until then, hardcode registers so that we can deal with their
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// aliases (because we don't have conditional byte moves).
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//
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BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::BH);
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BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::AH);
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BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
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BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
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BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
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BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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// NOTE: visitSetCondInst knows that the value is dumped into the BL
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// register at this point for long values...
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return isSigned;
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@ -664,21 +685,34 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
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unsigned OpNum = getSetCCNumber(I.getOpcode());
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unsigned DestReg = getReg(I);
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bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
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I.getOperand(1));
|
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MachineBasicBlock::iterator MII = BB->end();
|
||||
emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
|
||||
DestReg);
|
||||
}
|
||||
|
||||
if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
|
||||
/// emitSetCCOperation - Common code shared between visitSetCondInst and
|
||||
/// constant expression support.
|
||||
void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator &IP,
|
||||
Value *Op0, Value *Op1, unsigned Opcode,
|
||||
unsigned TargetReg) {
|
||||
unsigned OpNum = getSetCCNumber(Opcode);
|
||||
bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP);
|
||||
|
||||
if (getClassB(Op0->getType()) != cLong || OpNum < 2) {
|
||||
// Handle normal comparisons with a setcc instruction...
|
||||
BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
|
||||
BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
|
||||
} else {
|
||||
// Handle long comparisons by copying the value which is already in BL into
|
||||
// the register we want...
|
||||
BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
|
||||
BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
|
||||
/// operand, in the specified target register.
|
||||
void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
|
||||
@ -797,8 +831,9 @@ void ISel::visitBranchInst(BranchInst &BI) {
|
||||
}
|
||||
|
||||
unsigned OpNum = getSetCCNumber(SCI->getOpcode());
|
||||
MachineBasicBlock::iterator MII = BB->end();
|
||||
bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
|
||||
SCI->getOperand(1));
|
||||
SCI->getOperand(1), BB, MII);
|
||||
|
||||
// LLVM -> X86 signed X86 unsigned
|
||||
// ----- ---------- ------------
|
||||
|
||||
Loading…
Reference in New Issue
Block a user