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[SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195573 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1411,6 +1411,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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setOperationAction(ISD::ROTL , MVT::i64, Expand);
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setOperationAction(ISD::ROTL , MVT::i64, Expand);
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setOperationAction(ISD::ROTR , MVT::i64, Expand);
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setOperationAction(ISD::ROTR , MVT::i64, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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}
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}
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// FIXME: There are instructions available for ATOMIC_FENCE
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// FIXME: There are instructions available for ATOMIC_FENCE
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@@ -2289,20 +2290,23 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
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std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
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std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
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}
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}
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static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
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static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
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bool is64Bit) {
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SDValue Chain = Op.getOperand(0); // Legalize the chain.
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SDValue Chain = Op.getOperand(0); // Legalize the chain.
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SDValue Size = Op.getOperand(1); // Legalize the size.
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SDValue Size = Op.getOperand(1); // Legalize the size.
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EVT VT = Size->getValueType(0);
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SDLoc dl(Op);
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SDLoc dl(Op);
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unsigned SPReg = SP::O6;
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unsigned SPReg = SP::O6;
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
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SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
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SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
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Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
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Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
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// The resultant pointer is actually 16 words from the bottom of the stack,
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// The resultant pointer is actually 16 words from the bottom of the stack,
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// to provide a register spill area.
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// to provide a register spill area.
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SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
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unsigned regSpillArea = (is64Bit) ? 128 : 96;
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DAG.getConstant(96, MVT::i32));
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SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
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DAG.getConstant(regSpillArea, VT));
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SDValue Ops[2] = { NewVal, Chain };
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SDValue Ops[2] = { NewVal, Chain };
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return DAG.getMergeValues(Ops, 2, dl);
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return DAG.getMergeValues(Ops, 2, dl);
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}
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}
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@@ -2626,7 +2630,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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hasHardQuad);
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hasHardQuad);
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case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
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case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
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is64Bit);
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case ISD::LOAD: return LowerF128Load(Op, DAG);
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case ISD::LOAD: return LowerF128Load(Op, DAG);
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case ISD::STORE: return LowerF128Store(Op, DAG);
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case ISD::STORE: return LowerF128Store(Op, DAG);
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@@ -1,10 +1,20 @@
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; RUN: llc -march=sparc < %s | FileCheck %s
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; RUN: llc -march=sparc < %s | FileCheck %s --check-prefix=V8
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; RUN: llc -march=sparcv9 < %s | FileCheck %s --check-prefix=SPARC64
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; V8-LABEL: variable_alloca_with_adj_call_stack
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; V8: save %sp, -96, %sp
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; V8: add {{.+}}, 96, %o0
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; V8: add %sp, -16, %sp
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; V8: call foo
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; V8: add %sp, 16, %sp
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; SPARC64-LABEL: variable_alloca_with_adj_call_stack
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; SPARC64: save %sp, -128, %sp
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; SPARC64: add {{.+}}, 128, %o0
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; SPARC64: add %sp, -80, %sp
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; SPARC64: call foo
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; SPARC64: add %sp, 80, %sp
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; CHECK: variable_alloca_with_adj_call_stack
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; CHECK: save %sp, -96, %sp
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; CHECK: add %sp, -16, %sp
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; CHECK: call foo
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; CHECK: add %sp, 16, %sp
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define void @variable_alloca_with_adj_call_stack(i32 %num) {
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define void @variable_alloca_with_adj_call_stack(i32 %num) {
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entry:
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entry:
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%0 = alloca i8, i32 %num, align 8
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%0 = alloca i8, i32 %num, align 8
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