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Change SSE pack operation definitions to fit what the intrinsics expected.

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For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27254 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2006-03-29 23:53:14 +00:00
parent 4e27b8e8f4
commit 591f740a40
2 changed files with 23 additions and 23 deletions
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6
include/llvm/IntrinsicsX86.td
View File

@@ -288,13 +288,13 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Misc. // Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [InstrNoMem]>; llvm_v8i16_ty], [InstrNoMem]>;
def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">, def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
llvm_v4i32_ty], [InstrNoMem]>; llvm_v4i32_ty], [InstrNoMem]>;
def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">, def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [InstrNoMem]>; llvm_v8i16_ty], [InstrNoMem]>;
def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">, def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>; Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;

40
lib/Target/X86/X86InstrSSE.td
View File

@@ -1182,39 +1182,39 @@ let isTwoAddress = 1 in {
def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1, def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2), VR128:$src2),
"packsswb {$src2, $dst|$dst, $src2}", "packsswb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
(v8i16 VR128:$src1), VR128:$src1,
(v8i16 VR128:$src2))))]>; VR128:$src2)))]>;
def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1, def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2), i128mem:$src2),
"packsswb {$src2, $dst|$dst, $src2}", "packsswb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
(v8i16 VR128:$src1), VR128:$src1,
(loadv8i16 addr:$src2))))]>; (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1, def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2), VR128:$src2),
"packsswb {$src2, $dst|$dst, $src2}", "packssdw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
(v4i32 VR128:$src1), VR128:$src1,
(v4i32 VR128:$src2))))]>; VR128:$src2)))]>;
def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1, def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2), i128mem:$src2),
"packsswb {$src2, $dst|$dst, $src2}", "packssdw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
(v4i32 VR128:$src1), VR128:$src1,
(loadv4i32 addr:$src2))))]>; (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1, def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2), VR128:$src2),
"packuswb {$src2, $dst|$dst, $src2}", "packuswb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
(v8i16 VR128:$src1), VR128:$src1,
(v8i16 VR128:$src2))))]>; VR128:$src2)))]>;
def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1, def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2), i128mem:$src2),
"packuswb {$src2, $dst|$dst, $src2}", "packuswb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
(v8i16 VR128:$src1), VR128:$src1,
(loadv8i16 addr:$src2))))]>; (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
} }
// Shuffle and unpack instructions // Shuffle and unpack instructions