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ARM assembly parsing and encoding for VLD1 w/ writeback.

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Three entry register list variation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-10-24 23:26:05 +00:00
parent d8fa76d4be
commit 5921675ff5
5 changed files with 53 additions and 21 deletions
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12
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@@ -2070,10 +2070,14 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::VLD1q16wb_register:
case ARM::VLD1q32wb_register:
case ARM::VLD1q64wb_register:
case ARM::VLD1d8T_UPD:
case ARM::VLD1d16T_UPD:
case ARM::VLD1d32T_UPD:
case ARM::VLD1d64T_UPD:
case ARM::VLD1d8Twb_fixed:
case ARM::VLD1d8Twb_register:
case ARM::VLD1d16Twb_fixed:
case ARM::VLD1d16Twb_register:
case ARM::VLD1d32Twb_fixed:
case ARM::VLD1d32Twb_register:
case ARM::VLD1d64Twb_fixed:
case ARM::VLD1d64Twb_register:
case ARM::VLD1d8Q_UPD:
case ARM::VLD1d16Q_UPD:
case ARM::VLD1d32Q_UPD: