mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-01 15:17:25 +00:00
[Hexagon] Converting remaining ALU32/ALU intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -107,6 +107,26 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: r{{[0-9]+}}.l{{ *}}={{ *}}#48242
|
||||
|
||||
define void @test11() #0 {
|
||||
entry:
|
||||
%0 = load i32* @d, align 4
|
||||
%1 = tail call i32 @llvm.hexagon.A2.tfril(i32 %0, i32 48242)
|
||||
store i32 %1, i32* @d, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: r{{[0-9]+}}.h{{ *}}={{ *}}#50826
|
||||
|
||||
define void @test12() #0 {
|
||||
entry:
|
||||
%0 = load i32* @d, align 4
|
||||
%1 = tail call i32 @llvm.hexagon.A2.tfrih(i32 %0, i32 50826)
|
||||
store i32 %1, i32* @d, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.A2.add(i32, i32) #1
|
||||
declare i32 @llvm.hexagon.A2.sub(i32, i32) #1
|
||||
declare i32 @llvm.hexagon.A2.and(i32, i32) #1
|
||||
@@ -117,3 +137,5 @@ declare i32 @llvm.hexagon.A2.addi(i32, i32) #1
|
||||
declare i32 @llvm.hexagon.A2.andir(i32, i32) #1
|
||||
declare i32 @llvm.hexagon.A2.orir(i32, i32) #1
|
||||
declare i32 @llvm.hexagon.A2.subri(i32, i32)
|
||||
declare i32 @llvm.hexagon.A2.tfril(i32, i32) #1
|
||||
declare i32 @llvm.hexagon.A2.tfrih(i32, i32) #1
|
||||
|
||||
Reference in New Issue
Block a user