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Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231883 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -686,14 +686,6 @@ public:
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const MachineFunction &MF,
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const VirtRegMap *VRM = nullptr) const;
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/// avoidWriteAfterWrite - Return true if the register allocator should avoid
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/// writing a register from RC in two consecutive instructions.
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/// This can avoid pipeline stalls on certain architectures.
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/// It does cause increased register pressure, though.
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virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
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return false;
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}
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/// updateRegAllocHint - A callback to allow target a chance to update
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/// register allocation hints when a register is "changed" (e.g. coalesced)
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/// to another register. e.g. On ARM, some virtual registers should target
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@ -283,29 +283,6 @@ ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
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}
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}
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bool
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ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
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// CortexA9 has a Write-after-write hazard for NEON registers.
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if (!STI.isLikeA9())
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return false;
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switch (RC->getID()) {
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case ARM::DPRRegClassID:
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case ARM::DPR_8RegClassID:
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case ARM::DPR_VFP2RegClassID:
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case ARM::QPRRegClassID:
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case ARM::QPR_8RegClassID:
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case ARM::QPR_VFP2RegClassID:
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case ARM::SPRRegClassID:
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case ARM::SPR_8RegClassID:
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// Avoid reusing S, D, and Q registers.
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// Don't increase register pressure for QQ and QQQQ.
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return true;
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default:
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return false;
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}
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}
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bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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@ -138,8 +138,6 @@ public:
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void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const override;
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bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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