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[ARM] Add Thumb-2 code size optimization test for ASR (register).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216746 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2014-08-29 17:19:00 +00:00
parent b1424d72ca
commit 59758c4337
1 changed files with 9 additions and 0 deletions
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9
test/CodeGen/ARM/thumb2-size-opt.ll
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@ -18,3 +18,12 @@ entry:
%shr = ashr i32 %a, 13 %shr = ashr i32 %a, 13
ret i32 %shr ret i32 %shr
} }
define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone {
; CHECK-LABEL: "asr-reg":
; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
entry:
%shr = ashr i32 %a, %b
ret i32 %shr
}