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random tidying

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107612 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-07-05 05:36:21 +00:00
parent a5b412581c
commit 598751ed25
2 changed files with 43 additions and 41 deletions
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12
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -4858,11 +4858,16 @@ bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
void SelectionDAGBuilder::visitCall(const CallInst &I) {
// Handle inline assembly differently.
if (isa<InlineAsm>(I.getCalledValue())) {
visitInlineAsm(&I);
return;
}
const char *RenameFn = 0;
if (Function *F = I.getCalledFunction()) {
if (F->isDeclaration()) {
const TargetIntrinsicInfo *II = TM.getIntrinsicInfo();
if (II) {
if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
if (unsigned IID = II->getIntrinsicID(F)) {
RenameFn = visitIntrinsicCall(I, IID);
if (!RenameFn)
@ -4935,9 +4940,6 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
return;
}
}
} else if (isa<InlineAsm>(I.getCalledValue())) {
visitInlineAsm(&I);
return;
}
SDValue Callee;

68
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -609,9 +609,9 @@ bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
unsigned &NumIntermediates,
EVT &RegisterVT,
TargetLowering* TLI) {
unsigned &NumIntermediates,
EVT &RegisterVT,
TargetLowering *TLI) {
// Figure out the right, legal destination reg to copy into.
unsigned NumElts = VT.getVectorNumElements();
MVT EltTy = VT.getVectorElementType();
@ -736,39 +736,39 @@ void TargetLowering::computeRegisterProperties() {
for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
MVT VT = (MVT::SimpleValueType)i;
if (!isTypeLegal(VT)) {
MVT IntermediateVT;
EVT RegisterVT;
unsigned NumIntermediates;
NumRegistersForVT[i] =
getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
RegisterVT, this);
RegisterTypeForVT[i] = RegisterVT;
if (isTypeLegal(VT)) continue;
// Determine if there is a legal wider type.
bool IsLegalWiderType = false;
EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
EVT SVT = (MVT::SimpleValueType)nVT;
if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts && NElts != 1) {
TransformToType[i] = SVT;
ValueTypeActions.setTypeAction(VT, Promote);
IsLegalWiderType = true;
break;
}
MVT IntermediateVT;
EVT RegisterVT;
unsigned NumIntermediates;
NumRegistersForVT[i] =
getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
RegisterVT, this);
RegisterTypeForVT[i] = RegisterVT;
// Determine if there is a legal wider type.
bool IsLegalWiderType = false;
EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
EVT SVT = (MVT::SimpleValueType)nVT;
if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts && NElts != 1) {
TransformToType[i] = SVT;
ValueTypeActions.setTypeAction(VT, Promote);
IsLegalWiderType = true;
break;
}
if (!IsLegalWiderType) {
EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
TransformToType[i] = MVT::Other;
ValueTypeActions.setTypeAction(VT, Expand);
} else {
TransformToType[i] = NVT;
ValueTypeActions.setTypeAction(VT, Promote);
}
}
if (!IsLegalWiderType) {
EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
TransformToType[i] = MVT::Other;
ValueTypeActions.setTypeAction(VT, Expand);
} else {
TransformToType[i] = NVT;
ValueTypeActions.setTypeAction(VT, Promote);
}
}
}