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Make RegList an ASM operand so that TableGen will generate code for it. This is

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an initial implementation and may change once reglists are fully fleshed out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-08 00:39:58 +00:00
parent b32e7844e9
commit 5991487c10
1 changed files with 7 additions and 2 deletions
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9
lib/Target/ARM/ARMInstrInfo.td
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@ -282,6 +282,11 @@ def reglist : Operand<i32> {
let PrintMethod = "printRegisterList";
}
def RegListAsmOperand : AsmOperandClass {
let Name = "RegList";
let SuperClasses = [];
}
// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
def cpinst_operand : Operand<i32> {
let PrintMethod = "printCPInstOperand";
@ -454,7 +459,7 @@ def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
let PrintMethod = "printLdStmModeOperand";
}
def ARMMemMode5AsmOperand : AsmOperandClass {
def MemMode5AsmOperand : AsmOperandClass {
let Name = "MemMode5";
let SuperClasses = [];
}
@ -465,7 +470,7 @@ def addrmode5 : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode5", []> {
let PrintMethod = "printAddrMode5Operand";
let MIOperandInfo = (ops GPR:$base, i32imm);
let ParserMatchClass = ARMMemMode5AsmOperand;
let ParserMatchClass = MemMode5AsmOperand;
string EncoderMethod = "getAddrMode5OpValue";
}