6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-08 19:36:02 +00:00
Code Issues Projects Releases Wiki Activity

Use a SetTheory instance to expand register lists in register classes.

Browse Source 
This prepares tablegen to compute register lists from set theoretic dag
expressions. This doesn't really make any difference as long as
Target.td still declares RegisterClass::MemberList as [Register].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-15 05:09:20 +00:00
parent 31bfd9bc45
commit 59f26aadce
2 changed files with 13 additions and 5 deletions

9
utils/TableGen/CodeGenRegisters.cpp

@ -172,9 +172,9 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
}
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
Elements = R->getValueAsListOfDefs("MemberList");
for (unsigned i = 0, e = Elements.size(); i != e; ++i)
Members.insert(RegBank.getReg(Elements[i]));
Elements = RegBank.getSets().expand(R);
for (unsigned i = 0, e = Elements->size(); i != e; ++i)
Members.insert(RegBank.getReg((*Elements)[i]));
// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
ListInit *SRC = R->getValueAsListInit("SubRegClasses");
@ -240,6 +240,9 @@ const std::string &CodeGenRegisterClass::getName() const {
//===----------------------------------------------------------------------===//
CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
// Configure register Sets to understand register classes.
Sets.addFieldExpander("RegisterClass", "MemberList");
// Read in the user-defined (named) sub-register indices.
// More indices will be synthesized later.
SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");

9
utils/TableGen/CodeGenRegisters.h

@ -16,6 +16,7 @@
#define CODEGEN_REGISTERS_H
#include "Record.h"
#include "SetTheory.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
@ -84,7 +85,7 @@ namespace llvm {
class CodeGenRegisterClass {
CodeGenRegister::Set Members;
std::vector<Record*> Elements;
const std::vector<Record*> *Elements;
public:
Record *TheDef;
std::string Namespace;
@ -125,7 +126,7 @@ namespace llvm {
// Returns an ordered list of class members.
// The order of registers is the same as in the .td file.
ArrayRef<Record*> getOrder() const {
return Elements;
return *Elements;
}
CodeGenRegisterClass(CodeGenRegBank&, Record *R);
@ -135,6 +136,8 @@ namespace llvm {
// them.
class CodeGenRegBank {
RecordKeeper &Records;
SetTheory Sets;
std::vector<Record*> SubRegIndices;
unsigned NumNamedIndices;
std::vector<CodeGenRegister> Registers;
@ -154,6 +157,8 @@ namespace llvm {
public:
CodeGenRegBank(RecordKeeper&);
SetTheory &getSets() { return Sets; }
// Sub-register indices. The first NumNamedIndices are defined by the user
// in the .td files. The rest are synthesized such that all sub-registers
// have a unique name.