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[ARM64] Rename LR to the UAL-compliant 'X30'.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:43:59 +00:00
parent 37fe6627f6
commit 5a09ce9ad1
10 changed files with 29 additions and 29 deletions
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2
lib/Target/ARM64/ARM64RegisterInfo.td
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@@ -113,7 +113,7 @@ def X26 : ARM64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
def X27 : ARM64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>; def X27 : ARM64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
def X28 : ARM64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>; def X28 : ARM64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
def FP : ARM64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>; def FP : ARM64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
def LR : ARM64Reg<30, "lr", [W30]>, DwarfRegAlias<W30>; def LR : ARM64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
def SP : ARM64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>; def SP : ARM64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
def XZR : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>; def XZR : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
} }

2
lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
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@@ -1872,7 +1872,7 @@ int ARM64AsmParser::tryParseRegister() {
if (RegNum == 0) if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase) RegNum = StringSwitch<unsigned>(lowerCase)
.Case("fp", ARM64::FP) .Case("fp", ARM64::FP)
.Case("x30", ARM64::LR) .Case("lr", ARM64::LR)
.Case("x31", ARM64::XZR) .Case("x31", ARM64::XZR)
.Case("w31", ARM64::WZR) .Case("w31", ARM64::WZR)
.Default(0); .Default(0);

4
test/CodeGen/ARM64/frameaddr.ll
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@@ -3,10 +3,10 @@
define i8* @t() nounwind { define i8* @t() nounwind {
entry: entry:
; CHECK-LABEL: t: ; CHECK-LABEL: t:
; CHECK: stp x29, lr, [sp, #-16]! ; CHECK: stp x29, x30, [sp, #-16]!
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: mov x0, x29 ; CHECK: mov x0, x29
; CHECK: ldp x29, lr, [sp], #16 ; CHECK: ldp x29, x30, [sp], #16
; CHECK: ret ; CHECK: ret
%0 = call i8* @llvm.frameaddress(i32 0) %0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0 ret i8* %0

8
test/CodeGen/ARM64/hello.ll
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@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX ; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: stp x29, lr, [sp, #-16]! ; CHECK: stp x29, x30, [sp, #-16]!
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: stur wzr, [x29, #-4] ; CHECK-NEXT: stur wzr, [x29, #-4]
@@ -10,11 +10,11 @@
; CHECK: add x0, x0, L_.str@PAGEOFF ; CHECK: add x0, x0, L_.str@PAGEOFF
; CHECK-NEXT: bl _puts ; CHECK-NEXT: bl _puts
; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, lr, [sp], #16 ; CHECK-NEXT: ldp x29, x30, [sp], #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-LINUX-LABEL: main: ; CHECK-LINUX-LABEL: main:
; CHECK-LINUX: stp x29, lr, [sp, #-16]! ; CHECK-LINUX: stp x29, x30, [sp, #-16]!
; CHECK-LINUX-NEXT: mov x29, sp ; CHECK-LINUX-NEXT: mov x29, sp
; CHECK-LINUX-NEXT: sub sp, sp, #16 ; CHECK-LINUX-NEXT: sub sp, sp, #16
; CHECK-LINUX-NEXT: stur wzr, [x29, #-4] ; CHECK-LINUX-NEXT: stur wzr, [x29, #-4]
@@ -22,7 +22,7 @@
; CHECK-LINUX: add x0, x0, :lo12:.L.str ; CHECK-LINUX: add x0, x0, :lo12:.L.str
; CHECK-LINUX-NEXT: bl puts ; CHECK-LINUX-NEXT: bl puts
; CHECK-LINUX-NEXT: mov sp, x29 ; CHECK-LINUX-NEXT: mov sp, x29
; CHECK-LINUX-NEXT: ldp x29, lr, [sp], #16 ; CHECK-LINUX-NEXT: ldp x29, x30, [sp], #16
; CHECK-LINUX-NEXT: ret ; CHECK-LINUX-NEXT: ret
@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00" @.str = private unnamed_addr constant [7 x i8] c"hello\0A\00"

6
test/CodeGen/ARM64/returnaddr.ll
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@@ -3,7 +3,7 @@
define i8* @rt0(i32 %x) nounwind readnone { define i8* @rt0(i32 %x) nounwind readnone {
entry: entry:
; CHECK-LABEL: rt0: ; CHECK-LABEL: rt0:
; CHECK: mov x0, lr ; CHECK: mov x0, x30
; CHECK: ret ; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 0) %0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0 ret i8* %0
@@ -12,12 +12,12 @@ entry:
define i8* @rt2() nounwind readnone { define i8* @rt2() nounwind readnone {
entry: entry:
; CHECK-LABEL: rt2: ; CHECK-LABEL: rt2:
; CHECK: stp x29, lr, [sp, #-16]! ; CHECK: stp x29, x30, [sp, #-16]!
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: ldr x[[REG:[0-9]+]], [x29] ; CHECK: ldr x[[REG:[0-9]+]], [x29]
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]] ; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
; CHECK: ldr x0, [x[[REG2]], #8] ; CHECK: ldr x0, [x[[REG2]], #8]
; CHECK: ldp x29, lr, [sp], #16 ; CHECK: ldp x29, x30, [sp], #16
; CHECK: ret ; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 2) %0 = tail call i8* @llvm.returnaddress(i32 2)
ret i8* %0 ret i8* %0

4
test/MC/ARM64/elf-relocs.s
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@@ -14,7 +14,7 @@
// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym // CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
add x20, x30, #:tprel_lo12:sym add x20, x30, #:tprel_lo12:sym
// CHECK: add x20, lr, :tprel_lo12:sym // CHECK: add x20, x30, :tprel_lo12:sym
// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym // CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
add x9, x12, #:tprel_lo12_nc:sym add x9, x12, #:tprel_lo12_nc:sym
@@ -38,7 +38,7 @@
// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2 // CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
add x20, x30, #:tprel_lo12:sym+12 add x20, x30, #:tprel_lo12:sym+12
// CHECK: add x20, lr, :tprel_lo12:sym+12 // CHECK: add x20, x30, :tprel_lo12:sym+12
// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12 // CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
add x9, x12, #:tprel_lo12_nc:sym+54 add x9, x12, #:tprel_lo12_nc:sym+54

16
test/MC/ARM64/memory.s
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@@ -209,14 +209,14 @@ foo:
;----------------------------------------------------------------------------- ;-----------------------------------------------------------------------------
ldr x29, [x7, #8]! ldr x29, [x7, #8]!
ldr lr, [x7, #8]! ldr x30, [x7, #8]!
ldr b5, [x0, #1]! ldr b5, [x0, #1]!
ldr h6, [x0, #2]! ldr h6, [x0, #2]!
ldr s7, [x0, #4]! ldr s7, [x0, #4]!
ldr d8, [x0, #8]! ldr d8, [x0, #8]!
ldr q9, [x0, #16]! ldr q9, [x0, #16]!
str lr, [x7, #-8]! str x30, [x7, #-8]!
str x29, [x7, #-8]! str x29, [x7, #-8]!
str b5, [x0, #-1]! str b5, [x0, #-1]!
str h6, [x0, #-2]! str h6, [x0, #-2]!
@@ -225,14 +225,14 @@ foo:
str q9, [x0, #-16]! str q9, [x0, #-16]!
; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8] ; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
; CHECK: ldr lr, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8] ; CHECK: ldr x30, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c] ; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c] ; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc] ; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc]
; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc] ; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc]
; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c] ; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
; CHECK: str lr, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8] ; CHECK: str x30, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8] ; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c] ; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c] ; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
@@ -243,7 +243,7 @@ foo:
;----------------------------------------------------------------------------- ;-----------------------------------------------------------------------------
; post-indexed loads and stores ; post-indexed loads and stores
;----------------------------------------------------------------------------- ;-----------------------------------------------------------------------------
str lr, [x7], #-8 str x30, [x7], #-8
str x29, [x7], #-8 str x29, [x7], #-8
str b5, [x0], #-1 str b5, [x0], #-1
str h6, [x0], #-2 str h6, [x0], #-2
@@ -252,14 +252,14 @@ foo:
str q9, [x0], #-16 str q9, [x0], #-16
ldr x29, [x7], #8 ldr x29, [x7], #8
ldr lr, [x7], #8 ldr x30, [x7], #8
ldr b5, [x0], #1 ldr b5, [x0], #1
ldr h6, [x0], #2 ldr h6, [x0], #2
ldr s7, [x0], #4 ldr s7, [x0], #4
ldr d8, [x0], #8 ldr d8, [x0], #8
ldr q9, [x0], #16 ldr q9, [x0], #16
; CHECK: str lr, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8] ; CHECK: str x30, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8] ; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c] ; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c] ; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
@@ -268,7 +268,7 @@ foo:
; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c] ; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8] ; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
; CHECK: ldr lr, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8] ; CHECK: ldr x30, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c] ; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c] ; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc] ; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc]

4
test/MC/ARM64/tls-modifiers-darwin.s
View File

@@ -3,10 +3,10 @@
adrp x2, _var@TLVPPAGE adrp x2, _var@TLVPPAGE
ldr x0, [x15, _var@TLVPPAGEOFF] ldr x0, [x15, _var@TLVPPAGEOFF]
add lr, x0, _var@TLVPPAGEOFF add x30, x0, _var@TLVPPAGEOFF
; CHECK: adrp x2, _var@TLVPPAG ; CHECK: adrp x2, _var@TLVPPAG
; CHECK: ldr x0, [x15, _var@TLVPPAGEOFF] ; CHECK: ldr x0, [x15, _var@TLVPPAGEOFF]
; CHECK: add lr, x0, _var@TLVPPAGEOFF ; CHECK: add x30, x0, _var@TLVPPAGEOFF
; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var ; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var ; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var

4
test/MC/ARM64/tls-relocs.s
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@@ -119,7 +119,7 @@
ldrb w29, [x30, #:tprel_lo12:var] ldrb w29, [x30, #:tprel_lo12:var]
ldrsb x29, [x28, #:tprel_lo12_nc:var] ldrsb x29, [x28, #:tprel_lo12_nc:var]
// CHECK: ldrb w29, [lr, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] // CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1 // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] // CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1 // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
@@ -243,7 +243,7 @@
ldrb w29, [x30, #:dtprel_lo12:var] ldrb w29, [x30, #:dtprel_lo12:var]
ldrsb x29, [x28, #:dtprel_lo12_nc:var] ldrsb x29, [x28, #:dtprel_lo12_nc:var]
// CHECK: ldrb w29, [lr, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] // CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1 // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] // CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1 // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1

8
test/MC/Disassembler/ARM64/memory.txt
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@@ -211,7 +211,7 @@
0x09 0x0c 0xc1 0x3c 0x09 0x0c 0xc1 0x3c
# CHECK: ldr x29, [x7, #8]! # CHECK: ldr x29, [x7, #8]!
# CHECK: ldr lr, [x7, #8]! # CHECK: ldr x30, [x7, #8]!
# CHECK: ldr b5, [x0, #1]! # CHECK: ldr b5, [x0, #1]!
# CHECK: ldr h6, [x0, #2]! # CHECK: ldr h6, [x0, #2]!
# CHECK: ldr s7, [x0, #4]! # CHECK: ldr s7, [x0, #4]!
@@ -226,7 +226,7 @@
0x08 0x8c 0x1f 0xfc 0x08 0x8c 0x1f 0xfc
0x09 0x0c 0x9f 0x3c 0x09 0x0c 0x9f 0x3c
# CHECK: str lr, [x7, #-8]! # CHECK: str x30, [x7, #-8]!
# CHECK: str x29, [x7, #-8]! # CHECK: str x29, [x7, #-8]!
# CHECK: str b5, [x0, #-1]! # CHECK: str b5, [x0, #-1]!
# CHECK: str h6, [x0, #-2]! # CHECK: str h6, [x0, #-2]!
@@ -246,7 +246,7 @@
0x08 0x84 0x1f 0xfc 0x08 0x84 0x1f 0xfc
0x09 0x04 0x9f 0x3c 0x09 0x04 0x9f 0x3c
# CHECK: str lr, [x7], #-8 # CHECK: str x30, [x7], #-8
# CHECK: str x29, [x7], #-8 # CHECK: str x29, [x7], #-8
# CHECK: str b5, [x0], #-1 # CHECK: str b5, [x0], #-1
# CHECK: str h6, [x0], #-2 # CHECK: str h6, [x0], #-2
@@ -263,7 +263,7 @@
0x09 0x04 0xc1 0x3c 0x09 0x04 0xc1 0x3c
# CHECK: ldr x29, [x7], #8 # CHECK: ldr x29, [x7], #8
# CHECK: ldr lr, [x7], #8 # CHECK: ldr x30, [x7], #8
# CHECK: ldr b5, [x0], #1 # CHECK: ldr b5, [x0], #1
# CHECK: ldr h6, [x0], #2 # CHECK: ldr h6, [x0], #2
# CHECK: ldr s7, [x0], #4 # CHECK: ldr s7, [x0], #4