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Handle composed subreg indices when processing REQ_SEQUENCE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105066 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1136,14 +1136,13 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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static void UpdateRegSequenceSrcs(unsigned SrcReg,
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static void UpdateRegSequenceSrcs(unsigned SrcReg,
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unsigned DstReg, unsigned SubIdx,
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unsigned DstReg, unsigned SubIdx,
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MachineRegisterInfo *MRI) {
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MachineRegisterInfo *MRI,
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const TargetRegisterInfo &TRI) {
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for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
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for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
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RE = MRI->reg_end(); RI != RE; ) {
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RE = MRI->reg_end(); RI != RE; ) {
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MachineOperand &MO = RI.getOperand();
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MachineOperand &MO = RI.getOperand();
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++RI;
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++RI;
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MO.setReg(DstReg);
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MO.substVirtReg(DstReg, SubIdx, TRI);
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assert(MO.getSubReg() == 0);
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MO.setSubReg(SubIdx);
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}
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}
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}
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}
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@ -1315,7 +1314,7 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
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for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
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for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
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unsigned SrcReg = MI->getOperand(i).getReg();
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unsigned SrcReg = MI->getOperand(i).getReg();
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unsigned SubIdx = MI->getOperand(i+1).getImm();
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unsigned SubIdx = MI->getOperand(i+1).getImm();
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UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI);
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UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
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}
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}
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if (IsImpDef) {
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if (IsImpDef) {
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