6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-25 10:27:04 +00:00
Code Issues Projects Releases Wiki Activity

Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2012-08-01 07:39:18 +00:00
parent adfe2637b8
commit 5a2c607153
7 changed files with 71 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@@ -762,8 +762,7 @@ static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
translateRegister(mcInst, insn.vvvv);
return false;
case ENCODING_DUP:
return translateOperand(mcInst,
insn.spec->operands[operand.type - TYPE_DUP0],
return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
insn, Dis);
}
}
@@ -789,8 +788,8 @@ static bool translateInstruction(MCInst &mcInst,
insn.numImmediatesTranslated = 0;
for (index = 0; index < X86_MAX_OPERANDS; ++index) {
if (insn.spec->operands[index].encoding != ENCODING_NONE) {
if (translateOperand(mcInst, insn.spec->operands[index], insn, Dis)) {
if (insn.operands[index].encoding != ENCODING_NONE) {
if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
return true;
}
}

3
lib/Target/X86/Disassembler/X86Disassembler.h
View File

@@ -74,7 +74,8 @@
#ifndef X86DISASSEMBLER_H
#define X86DISASSEMBLER_H
#define INSTRUCTION_SPECIFIER_FIELDS
#define INSTRUCTION_SPECIFIER_FIELDS \
uint16_t operands;
#define INSTRUCTION_IDS \
unsigned instructionIDs;

16
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
View File

@@ -1495,14 +1495,14 @@ static int readOperands(struct InternalInstruction* insn) {
needVVVV = hasVVVV && (insn->vvvv != 0);
for (index = 0; index < X86_MAX_OPERANDS; ++index) {
switch (insn->spec->operands[index].encoding) {
switch (x86OperandSets[insn->spec->operands][index].encoding) {
case ENCODING_NONE:
break;
case ENCODING_REG:
case ENCODING_RM:
if (readModRM(insn))
return -1;
if (fixupReg(insn, &insn->spec->operands[index]))
if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
return -1;
break;
case ENCODING_CB:
@@ -1524,14 +1524,14 @@ static int readOperands(struct InternalInstruction* insn) {
}
if (readImmediate(insn, 1))
return -1;
if (insn->spec->operands[index].type == TYPE_IMM3 &&
if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
insn->immediates[insn->numImmediatesConsumed - 1] > 7)
return -1;
if (insn->spec->operands[index].type == TYPE_IMM5 &&
if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
insn->immediates[insn->numImmediatesConsumed - 1] > 31)
return -1;
if (insn->spec->operands[index].type == TYPE_XMM128 ||
insn->spec->operands[index].type == TYPE_XMM256)
if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
sawRegImm = 1;
break;
case ENCODING_IW:
@@ -1582,7 +1582,7 @@ static int readOperands(struct InternalInstruction* insn) {
needVVVV = 0; /* Mark that we have found a VVVV operand. */
if (!hasVVVV)
return -1;
if (fixupReg(insn, &insn->spec->operands[index]))
if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
return -1;
break;
case ENCODING_DUP:
@@ -1644,6 +1644,8 @@ int decodeInstruction(struct InternalInstruction* insn,
insn->instructionID == 0 ||
readOperands(insn))
return -1;
insn->operands = &x86OperandSets[insn->spec->operands][0];
insn->length = insn->readerCursor - insn->startLocation;

5
lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
View File

@@ -20,7 +20,8 @@
extern "C" {
#endif
#define INSTRUCTION_SPECIFIER_FIELDS
#define INSTRUCTION_SPECIFIER_FIELDS \
uint16_t operands;
#define INSTRUCTION_IDS \
unsigned instructionIDs;
@@ -538,6 +539,8 @@ struct InternalInstruction {
SIBIndex sibIndex;
uint8_t sibScale;
SIBBase sibBase;
const struct OperandSpecifier *operands;
};
/* decodeInstruction - Decode one instruction and store the decoding results in

1
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
View File

@@ -374,7 +374,6 @@ typedef enum {
struct InstructionSpecifier {
uint8_t modifierType;
uint8_t modifierBase;
struct OperandSpecifier operands[X86_MAX_OPERANDS];
/* The macro below must be defined wherever this file is included. */
INSTRUCTION_SPECIFIER_FIELDS