6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-10 04:33:40 +00:00
Code Issues Projects Releases Wiki Activity

Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stuart Hastings 2010-04-28 00:35:10 +00:00
parent 2d4b8ee1d9
commit 5a6a65be46
1 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lib/Target/X86/X86ISelLowering.cpp
View File

@ -5918,15 +5918,20 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
unsigned NumOperands = 0;
switch (Op.getNode()->getOpcode()) {
case ISD::ADD:
// Due to an isel shortcoming, be conservative if this add is likely to
// be selected as part of a load-modify-store instruction. When the root
// node in a match is a store, isel doesn't know how to remap non-chain
// non-flag uses of other nodes in the match, such as the ADD in this
// case. This leads to the ADD being left around and reselected, with
// the result being two adds in the output.
// Due to an isel shortcoming, be conservative if this add is
// likely to be selected as part of a load-modify-store
// instruction. When the root node in a match is a store, isel
// doesn't know how to remap non-chain non-flag uses of other
// nodes in the match, such as the ADD in this case. This leads
// to the ADD being left around and reselected, with the result
// being two adds in the output. Alas, even if none our users
// are stores, that doesn't prove we're O.K. Ergo, if we have
// any parents that aren't CopyToReg or SETCC, eschew INC/DEC.
// A better fix seems to require climbing the DAG back to the
// root, and it doesn't seem to be worth the effort.
for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
UE = Op.getNode()->use_end(); UI != UE; ++UI)
if (UI->getOpcode() == ISD::STORE)
if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
goto default_case;
if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {