mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-03 13:31:05 +00:00
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
5974c31acb
commit
5a7dd43f04
@ -403,16 +403,16 @@ class LoadM16_pat<PatFrag OpNode, Instruction I> :
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def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
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def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
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def: LoadM16_pat<sextloadi16_a, LhRxRyOffMemX16>;
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def: LoadM16_pat<zextloadi16_a, LhuRxRyOffMemX16>;
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def: LoadM16_pat<load_a, LwRxRyOffMemX16>;
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def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
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def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
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def: LoadM16_pat<load, LwRxRyOffMemX16>;
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class StoreM16_pat<PatFrag OpNode, Instruction I> :
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Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>;
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def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
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def: StoreM16_pat<truncstorei16_a, ShRxRyOffMemX16>;
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def: StoreM16_pat<store_a, SwRxRyOffMemX16>;
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def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
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def: StoreM16_pat<store, SwRxRyOffMemX16>;
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// Jump and Link (Call)
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@ -127,24 +127,15 @@ let DecoderNamespace = "Mips64" in {
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/// aligned
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defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
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defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
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defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
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defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
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defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
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defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
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defm LH64 : LoadM64<0x21, "lh", sextloadi16>;
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defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>;
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defm LW64 : LoadM64<0x23, "lw", sextloadi32>;
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defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>;
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defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
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defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
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defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
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defm LD : LoadM64<0x37, "ld", load_a>;
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defm SD : StoreM64<0x3f, "sd", store_a>;
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/// unaligned
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defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
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defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
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defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
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defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
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defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
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defm ULD : LoadM64<0x37, "uld", load_u, 1>;
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defm USD : StoreM64<0x3f, "usd", store_u, 1>;
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defm SH64 : StoreM64<0x29, "sh", truncstorei16>;
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defm SW64 : StoreM64<0x2b, "sw", truncstorei32>;
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defm LD : LoadM64<0x37, "ld", load>;
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defm SD : StoreM64<0x3f, "sd", store>;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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@ -244,21 +235,14 @@ let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>;
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def : MipsPat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>;
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>;
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def : MipsPat<(zextloadi32_u addr:$a),
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(DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>;
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
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}
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// hi/lo relocs
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@ -218,15 +218,9 @@ unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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return getMipsRegisterNumbering(MO.getReg());
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else if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isGlobal()) {
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if (MI.getOpcode() == Mips::ULW || MI.getOpcode() == Mips::USW ||
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MI.getOpcode() == Mips::ULH || MI.getOpcode() == Mips::ULHu)
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emitGlobalAddressUnaligned(MO.getGlobal(), getRelocation(MI, MO), 4);
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else if (MI.getOpcode() == Mips::USH)
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emitGlobalAddressUnaligned(MO.getGlobal(), getRelocation(MI, MO), 8);
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else
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emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true);
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} else if (MO.isSymbol())
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else if (MO.isGlobal())
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emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true);
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else if (MO.isSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));
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else if (MO.isCPI())
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emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO));
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@ -383,29 +377,8 @@ void MipsCodeEmitter::emitInstruction(const MachineInstr &MI) {
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if ((MI.getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo)
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return;
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switch (MI.getOpcode()) {
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case Mips::USW:
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NumEmitted += emitUSW(MI);
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break;
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case Mips::ULW:
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NumEmitted += emitULW(MI);
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break;
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case Mips::ULH:
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NumEmitted += emitULH(MI);
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break;
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case Mips::ULHu:
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NumEmitted += emitULHu(MI);
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break;
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case Mips::USH:
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NumEmitted += emitUSH(MI);
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break;
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default:
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emitWordLE(getBinaryCodeForInstr(MI));
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++NumEmitted; // Keep track of the # of mi's emitted
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break;
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}
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emitWordLE(getBinaryCodeForInstr(MI));
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++NumEmitted; // Keep track of the # of mi's emitted
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MCE.processDebugLoc(MI.getDebugLoc(), false);
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}
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@ -540,6 +540,15 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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return RegOpnd;
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}
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#ifndef NDEBUG
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case ISD::LOAD:
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case ISD::STORE:
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assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
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cast<MemSDNode>(Node)->getAlignment() &&
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"Unexpected unaligned loads/stores.");
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break;
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#endif
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case MipsISD::ThreadPointer: {
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EVT PtrVT = TLI.getPointerTy();
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unsigned RdhwrOpc, SrcReg, DestReg;
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@ -90,13 +90,13 @@ def fpimm0neg : PatLeaf<(fpimm), [{
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let DecoderMethod = "DecodeFMem" in {
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class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
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FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
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!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))],
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!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
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IILoad>;
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// FP store.
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class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
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FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
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!strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)],
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!strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
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IIStore>;
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}
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// FP indexed load.
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@ -282,26 +282,26 @@ let Predicates = [NotN64, NotMips64, HasStandardEncoding] in {
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// Indexed loads and stores.
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let Predicates = [HasMips32r2Or64, HasStandardEncoding] in {
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def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
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def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
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def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>;
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def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>;
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}
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let Predicates = [HasMips32r2, NotMips64, HasStandardEncoding] in {
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def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>;
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def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
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def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load>;
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def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store>;
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}
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let Predicates = [HasMips64, NotN64, HasStandardEncoding], DecoderNamespace="Mips64" in {
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def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
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def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
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def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load>;
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def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store>;
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}
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// n64
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let Predicates = [IsN64, HasStandardEncoding], isCodeGenOnly=1 in {
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def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
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def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
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def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>;
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def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>;
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def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load>;
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def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load>;
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def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store>;
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def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store>;
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}
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// Load/store doubleword indexed unaligned.
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@ -292,55 +292,6 @@ def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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def addr :
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ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
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//===----------------------------------------------------------------------===//
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// Pattern fragment for load/store
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//===----------------------------------------------------------------------===//
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class UnalignedLoad<PatFrag Node> :
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PatFrag<(ops node:$ptr), (Node node:$ptr), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
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}]>;
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class AlignedLoad<PatFrag Node> :
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PatFrag<(ops node:$ptr), (Node node:$ptr), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
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}]>;
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class UnalignedStore<PatFrag Node> :
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PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
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StoreSDNode *SD = cast<StoreSDNode>(N);
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return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
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}]>;
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class AlignedStore<PatFrag Node> :
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PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
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StoreSDNode *SD = cast<StoreSDNode>(N);
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return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
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}]>;
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// Load/Store PatFrags.
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def sextloadi16_a : AlignedLoad<sextloadi16>;
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def zextloadi16_a : AlignedLoad<zextloadi16>;
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def extloadi16_a : AlignedLoad<extloadi16>;
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def load_a : AlignedLoad<load>;
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def sextloadi32_a : AlignedLoad<sextloadi32>;
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def zextloadi32_a : AlignedLoad<zextloadi32>;
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def extloadi32_a : AlignedLoad<extloadi32>;
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def truncstorei16_a : AlignedStore<truncstorei16>;
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def store_a : AlignedStore<store>;
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def truncstorei32_a : AlignedStore<truncstorei32>;
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def sextloadi16_u : UnalignedLoad<sextloadi16>;
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def zextloadi16_u : UnalignedLoad<zextloadi16>;
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def extloadi16_u : UnalignedLoad<extloadi16>;
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def load_u : UnalignedLoad<load>;
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def sextloadi32_u : UnalignedLoad<sextloadi32>;
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def zextloadi32_u : UnalignedLoad<zextloadi32>;
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def extloadi32_u : UnalignedLoad<extloadi32>;
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def truncstorei16_u : UnalignedStore<truncstorei16>;
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def store_u : UnalignedStore<store>;
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def truncstorei32_u : UnalignedStore<truncstorei32>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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@ -957,19 +908,12 @@ let Predicates = [HasMips32r2, HasStandardEncoding] in {
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/// aligned
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defm LB : LoadM32<0x20, "lb", sextloadi8>;
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defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
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defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
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defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
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defm LW : LoadM32<0x23, "lw", load_a>;
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defm LH : LoadM32<0x21, "lh", sextloadi16>;
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defm LHu : LoadM32<0x25, "lhu", zextloadi16>;
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defm LW : LoadM32<0x23, "lw", load>;
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defm SB : StoreM32<0x28, "sb", truncstorei8>;
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defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
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defm SW : StoreM32<0x2b, "sw", store_a>;
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/// unaligned
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defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
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defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
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defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
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defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
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defm USW : StoreM32<0x2b, "usw", store_u, 1>;
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defm SH : StoreM32<0x29, "sh", truncstorei16>;
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defm SW : StoreM32<0x2b, "sw", store>;
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/// load/store left/right
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defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
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@ -1181,24 +1125,20 @@ def : MipsPat<(not CPURegs:$in),
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
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def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
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def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
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def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
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def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
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def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
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def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
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def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
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def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
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}
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// peepholes
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
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def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
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def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
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def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
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}
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// brcond patterns
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