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ARM-mode eh.sjlj.longjmp MC lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114896 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1920,6 +1920,60 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
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}
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return;
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}
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case ARM::Int_eh_sjlj_longjmp: {
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// ldr sp, [$src, #8]
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// ldr $scratch, [$src, #4]
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// ldr r7, [$src]
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// bx $scratch
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unsigned SrcReg = MI->getOperand(0).getReg();
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unsigned ScratchReg = MI->getOperand(1).getReg();
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::LDR);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
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TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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TmpInst.addOperand(MCOperand::CreateImm(8));
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// Predicate.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::LDR);
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TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
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TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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TmpInst.addOperand(MCOperand::CreateImm(4));
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// Predicate.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::LDR);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
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TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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// Predicate.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::BRIND);
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TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
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// Predicate.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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return;
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}
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}
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MCInst TmpInst;
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