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[ARM] Add v8.1a "Privileged Access Never" extension

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Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8504


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235087 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Sukharev
2015-04-16 11:34:25 +00:00
parent 0b86f54604
commit 5ade5fcee4
7 changed files with 159 additions and 3 deletions
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52
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -212,6 +212,10 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
@ -2119,6 +2123,54 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned Pred = fieldFromInstruction(Insn, 28, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4);
if (Pred == 0xF)
return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned Imm = fieldFromInstruction(Insn, 9, 1);
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
if ((FeatureBits & ARM::HasV8_1aOps) == 0 ||
(FeatureBits & ARM::HasV8Ops) == 0 )
return MCDisassembler::Fail;
// Decoder can be called from DecodeTST, which does not check the full
// encoding is valid.
if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
fieldFromInstruction(Insn, 4,4) != 0)
return MCDisassembler::Fail;
if (fieldFromInstruction(Insn, 10,10) != 0 ||
fieldFromInstruction(Insn, 0,4) != 0)
S = MCDisassembler::SoftFail;
Inst.setOpcode(ARM::SETPAN);
Inst.addOperand(MCOperand::CreateImm(Imm));
return S;
}
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;