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R600: Enable -verify-machineinstrs in some tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-10-01 19:32:38 +00:00
parent db3de10637
commit 5b00e833fa
10 changed files with 24 additions and 14 deletions
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2
lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -28,7 +28,7 @@
using namespace llvm;
AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
: AMDGPUGenInstrInfo(0,0), RI(tm), TM(tm) { }
: AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { }
const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
return RI;

10
lib/Target/R600/AMDILInstrInfo.td
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@ -118,15 +118,15 @@ class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
// Multiclass Instruction formats
//===--------------------------------------------------------------------===//
// Multiclass that handles branch instructions
multiclass BranchConditional<SDNode Op> {
multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
def _i32 : ILFormat<(outs),
(ins brtarget:$target, GPRI32:$src0),
(ins brtarget:$target, rci:$src0),
"; i32 Pseudo branch instruction",
[(Op bb:$target, GPRI32:$src0)]>;
[(Op bb:$target, (i32 rci:$src0))]>;
def _f32 : ILFormat<(outs),
(ins brtarget:$target, GPRF32:$src0),
(ins brtarget:$target, rcf:$src0),
"; f32 Pseudo branch instruction",
[(Op bb:$target, GPRF32:$src0)]>;
[(Op bb:$target, (f32 rcf:$src0))]>;
}
// Only scalar types should generate flow control

9
lib/Target/R600/R600InstrInfo.cpp
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@ -651,6 +651,11 @@ bool isJump(unsigned Opcode) {
return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
}
static bool isBranch(unsigned Opcode) {
return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
Opcode == AMDGPU::BRANCH_COND_f32;
}
bool
R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
@ -669,6 +674,10 @@ R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
return false;
--I;
}
// AMDGPU::BRANCH* instructions are only available after isel and are not
// handled
if (isBranch(I->getOpcode()))
return true;
if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
return false;
}

2
lib/Target/R600/R600Instructions.td
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@ -2238,7 +2238,7 @@ let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
def BRANCH : ILFormat<(outs), (ins brtarget:$target),
"; Pseudo unconditional branch instruction",
[(br bb:$target)]>;
defm BRANCH_COND : BranchConditional<IL_brcond>;
defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;
}
//===---------------------------------------------------------------------===//

5
lib/Target/R600/R600RegisterInfo.td
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@ -138,8 +138,6 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X",
def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
(add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>;
} // End isAllocatable = 0
def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC0_%u_X", 128, 159))>;
@ -172,6 +170,8 @@ def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
(interleave R600_KC1_X, R600_KC1_Y,
R600_KC1_Z, R600_KC1_W)>;
} // End isAllocatable = 0
def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "T%u_X", 0, 127), AR_X)>;
@ -192,6 +192,7 @@ def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
R600_TReg32,
R600_ArrayBase,
R600_Addr,
R600_KC0, R600_KC1,
ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
ALU_CONST, ALU_PARAM, OQAP
)>;

2
test/CodeGen/R600/schedule-fs-loop-nested-if.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts
define void @main() {

2
test/CodeGen/R600/schedule-fs-loop-nested.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts
define void @main() {

2
test/CodeGen/R600/schedule-fs-loop.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts
define void @main() {

2
test/CodeGen/R600/schedule-if-2.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts
define void @main() {

2
test/CodeGen/R600/schedule-if.ll
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@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts
define void @main() {