6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 04:33:05 +00:00
Code Issues Projects Releases Wiki Activity

Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-08-10 22:47:03 +00:00
parent 698fbd5b94
commit 5b5708106e
12 changed files with 879 additions and 879 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
lib/Target/PowerPC/PPC32AsmPrinter.cpp
View File

@ -478,16 +478,16 @@ void Printer::printOp(const MachineOperand &MO,
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
O << (short)Imm;
} else if (ArgType == PPC32II::Zimm16) {
} else if (ArgType == PPCII::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
/// printMachineInstruction -- Print out a single PPC LLVM instruction
/// MI in Darwin syntax to the current output stream.
///
void Printer::printMachineInstruction(const MachineInstr *MI) {
@ -498,15 +498,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned ArgCount = MI->getNumOperands();
unsigned ArgType[] = {
(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask
(Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
};
assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
"Instruction requires VMX support");
assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
"Instruction requires 64 bit support");
++EmittedInsts;
@ -514,27 +514,27 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are
// holding arguments to the called function.
if (Opcode == PPC32::COND_BRANCH) {
if (Opcode == PPC::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
} else if (Opcode == PPC32::IMPLICIT_DEF) {
} else if (Opcode == PPC::IMPLICIT_DEF) {
O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0));
O << "\n";
return;
} else if (Opcode == PPC32::CALLpcrel) {
} else if (Opcode == PPC::CALLpcrel) {
O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0));
O << "\n";
return;
} else if (Opcode == PPC32::CALLindirect) {
} else if (Opcode == PPC::CALLindirect) {
O << TII.getName(Opcode) << " ";
printImmOp(MI->getOperand(0), ArgType[0]);
O << ", ";
printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n";
return;
} else if (Opcode == PPC32::MovePCtoLR) {
} else if (Opcode == PPC::MovePCtoLR) {
// FIXME: should probably be converted to cout.width and cout.fill
O << "bl \"L0000" << LabelNumber << "$pb\"\n";
O << "\"L0000" << LabelNumber << "$pb\":\n";
@ -545,34 +545,34 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
}
O << TII.getName(Opcode) << " ";
if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) {
printOp(MI->getOperand(0));
O << ", lo16(";
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")";
O << "(";
if (MI->getOperand(1).getReg() == PPC32::R0)
if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ")\n";
} else if (Opcode == PPC32::LOADHiAddr) {
} else if (Opcode == PPC::LOADHiAddr) {
printOp(MI->getOperand(0));
O << ", ";
if (MI->getOperand(1).getReg() == PPC32::R0)
if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ", ha16(" ;
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")\n";
} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
} else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
printOp(MI->getOperand(0));
O << ", ";
printImmOp(MI->getOperand(1), ArgType[1]);
O << "(";
if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC32::R0)
MI->getOperand(2).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(2));
@ -580,9 +580,9 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
} else {
for (i = 0; i < ArgCount; ++i) {
// addi and friends
if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
MI->getOperand(1).hasAllocatedReg() &&
MI->getOperand(1).getReg() == PPC32::R0) {
MI->getOperand(1).getReg() == PPC::R0) {
O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&

744
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

File diff suppressed because it is too large Load Diff

46
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -478,16 +478,16 @@ void Printer::printOp(const MachineOperand &MO,
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
O << (short)Imm;
} else if (ArgType == PPC32II::Zimm16) {
} else if (ArgType == PPCII::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
/// printMachineInstruction -- Print out a single PPC LLVM instruction
/// MI in Darwin syntax to the current output stream.
///
void Printer::printMachineInstruction(const MachineInstr *MI) {
@ -498,15 +498,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned ArgCount = MI->getNumOperands();
unsigned ArgType[] = {
(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask
(Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
};
assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
"Instruction requires VMX support");
assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
"Instruction requires 64 bit support");
++EmittedInsts;
@ -514,27 +514,27 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are
// holding arguments to the called function.
if (Opcode == PPC32::COND_BRANCH) {
if (Opcode == PPC::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
} else if (Opcode == PPC32::IMPLICIT_DEF) {
} else if (Opcode == PPC::IMPLICIT_DEF) {
O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0));
O << "\n";
return;
} else if (Opcode == PPC32::CALLpcrel) {
} else if (Opcode == PPC::CALLpcrel) {
O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0));
O << "\n";
return;
} else if (Opcode == PPC32::CALLindirect) {
} else if (Opcode == PPC::CALLindirect) {
O << TII.getName(Opcode) << " ";
printImmOp(MI->getOperand(0), ArgType[0]);
O << ", ";
printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n";
return;
} else if (Opcode == PPC32::MovePCtoLR) {
} else if (Opcode == PPC::MovePCtoLR) {
// FIXME: should probably be converted to cout.width and cout.fill
O << "bl \"L0000" << LabelNumber << "$pb\"\n";
O << "\"L0000" << LabelNumber << "$pb\":\n";
@ -545,34 +545,34 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
}
O << TII.getName(Opcode) << " ";
if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) {
printOp(MI->getOperand(0));
O << ", lo16(";
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")";
O << "(";
if (MI->getOperand(1).getReg() == PPC32::R0)
if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ")\n";
} else if (Opcode == PPC32::LOADHiAddr) {
} else if (Opcode == PPC::LOADHiAddr) {
printOp(MI->getOperand(0));
O << ", ";
if (MI->getOperand(1).getReg() == PPC32::R0)
if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ", ha16(" ;
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")\n";
} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
} else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
printOp(MI->getOperand(0));
O << ", ";
printImmOp(MI->getOperand(1), ArgType[1]);
O << "(";
if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC32::R0)
MI->getOperand(2).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(2));
@ -580,9 +580,9 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
} else {
for (i = 0; i < ArgCount; ++i) {
// addi and friends
if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
MI->getOperand(1).hasAllocatedReg() &&
MI->getOperand(1).getReg() == PPC32::R0) {
MI->getOperand(1).getReg() == PPC::R0) {
O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&

16
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -35,17 +35,17 @@ namespace {
///
static unsigned bytesForOpcode(unsigned opcode) {
switch (opcode) {
case PPC32::COND_BRANCH:
case PPC::COND_BRANCH:
// while this will be 4 most of the time, if we emit 12 it is just a
// minor pessimization that saves us from having to worry about
// keeping the offsets up to date later when we emit long branch glue.
return 12;
case PPC32::MovePCtoLR:
case PPC::MovePCtoLR:
// MovePCtoLR is actually a combination of a branch-and-link (bl)
// followed by a move from link register to dest reg (mflr)
return 8;
break;
case PPC32::IMPLICIT_DEF: // no asm emitted
case PPC::IMPLICIT_DEF: // no asm emitted
return 0;
break;
default:
@ -91,7 +91,7 @@ namespace {
for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
MBBI != EE; ++MBBI) {
if (MBBI->getOpcode() == PPC32::COND_BRANCH) {
if (MBBI->getOpcode() == PPC::COND_BRANCH) {
// condbranch operands:
// 0. CR0 register
// 1. bc opcode
@ -108,11 +108,11 @@ namespace {
MachineInstr *MI = MBBI;
if (Displacement >= -32768 && Displacement <= 32767) {
BuildMI(*MBB, MBBI, Opcode, 2).addReg(PPC32::CR0).addMBB(trueMBB);
BuildMI(*MBB, MBBI, Opcode, 2).addReg(PPC::CR0).addMBB(trueMBB);
} else {
BuildMI(*MBB, MBBI, Inverted, 2).addReg(PPC32::CR0).addSImm(8);
BuildMI(*MBB, MBBI, PPC32::B, 1).addMBB(trueMBB);
BuildMI(*MBB, MBBI, PPC32::B, 1).addMBB(falseMBB);
BuildMI(*MBB, MBBI, Inverted, 2).addReg(PPC::CR0).addSImm(8);
BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(trueMBB);
BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(falseMBB);
}
MBB->erase(MI);
}

32
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -42,7 +42,7 @@ def Vpr : Format<22>;
//
// PowerPC instruction formats
class PPC32I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
class I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
field bits<32> Inst;
bits<3> ArgCount;
@ -55,13 +55,13 @@ class PPC32I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
bit VMX = vmx;
let Name = name;
let Namespace = "PPC32";
let Namespace = "PPC";
let Inst{0-5} = opcode;
}
// 1.7.1 I-Form
class IForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<24> LI;
let ArgCount = 1;
@ -78,7 +78,7 @@ class IForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
// 1.7.2 B-Form
class BForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<5> BO;
field bits<5> BI;
field bits<14> BD;
@ -110,7 +110,7 @@ class BForm_ext<string name, bits<6> opcode, bit aa, bit lk, bits<5> bo,
// 1.7.4 D-Form
class DForm_base<string name, bits<6> opcode, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<5> A;
field bits<5> B;
field bits<16> C;
@ -162,7 +162,7 @@ class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx>
}
class DForm_5<string name, bits<6> opcode, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<3> BF;
field bits<1> L;
field bits<5> RA;
@ -224,7 +224,7 @@ class DForm_9<string name, bits<6> opcode, bit ppc64, bit vmx>
// 1.7.6 X-Form
class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc,
bit ppc64, bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
let ArgCount = 3;
field bits<5> ST;
field bits<5> A;
@ -278,7 +278,7 @@ class XForm_11<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
}
class XForm_16<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<3> BF;
field bits<1> L;
field bits<5> RA;
@ -306,7 +306,7 @@ class XForm_16_ext<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
}
class XForm_17<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<3> BF;
field bits<5> FRA;
field bits<5> FRB;
@ -356,7 +356,7 @@ class XLForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
}
class XLForm_2<string name, bits<6> opcode, bits<10> xo, bit lk, bit ppc64,
bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
bit vmx> : I<name, opcode, ppc64, vmx> {
field bits<5> BO;
field bits<5> BI;
field bits<2> BH;
@ -390,7 +390,7 @@ class XLForm_2_ext<string name, bits<6> opcode, bits<10> xo, bits<5> bo,
// 1.7.8 XFX-Form
class XFXForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
field bits<5> ST;
field bits<10> SPR;
@ -428,7 +428,7 @@ class XFXForm_7_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
// 1.7.11 XO-Form
class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
bit ppc64, bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
field bits<5> RT;
field bits<5> RA;
field bits<5> RB;
@ -468,7 +468,7 @@ class XOForm_3<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
// 1.7.12 A-Form
class AForm_1<string name, bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
bit vmx> : I<name, opcode, ppc64, vmx> {
let ArgCount = 4;
field bits<5> FRT;
field bits<5> FRA;
@ -514,7 +514,7 @@ class AForm_4<string name, bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
// 1.7.13 M-Form
class MForm_1<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
: PPC32I<name, opcode, ppc64, vmx> {
: I<name, opcode, ppc64, vmx> {
let ArgCount = 5;
field bits<5> RS;
field bits<5> RA;
@ -543,7 +543,7 @@ class MForm_2<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
//===----------------------------------------------------------------------===//
class Pseudo<string name> : PPC32I<name, 0, 0, 0> {
class Pseudo<string name> : I<name, 0, 0, 0> {
let Name = name;
let ArgCount = 0;
let PPC64 = 0;
@ -555,5 +555,5 @@ class Pseudo<string name> : PPC32I<name, 0, 0, 0> {
let Arg3Type = Pseudo.Value;
let Arg4Type = 0;
let Inst {31-0} = 0;
let Inst{31-0} = 0;
}

2
lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
class PPCReg : Register {
let Namespace = "PPC32";
let Namespace = "PPC";
}
// We identify all our registers with a 5-bit ID, for consistency's sake.

46
lib/Target/PowerPC/PowerPCAsmPrinter.cpp
View File

@ -478,16 +478,16 @@ void Printer::printOp(const MachineOperand &MO,
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
O << (short)Imm;
} else if (ArgType == PPC32II::Zimm16) {
} else if (ArgType == PPCII::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
/// printMachineInstruction -- Print out a single PPC LLVM instruction
/// MI in Darwin syntax to the current output stream.
///
void Printer::printMachineInstruction(const MachineInstr *MI) {
@ -498,15 +498,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned ArgCount = MI->getNumOperands();
unsigned ArgType[] = {
(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask
(Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
(Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
};
assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
"Instruction requires VMX support");
assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
"Instruction requires 64 bit support");
++EmittedInsts;
@ -514,27 +514,27 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are
// holding arguments to the called function.
if (Opcode == PPC32::COND_BRANCH) {
if (Opcode == PPC::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
} else if (Opcode == PPC32::IMPLICIT_DEF) {
} else if (Opcode == PPC::IMPLICIT_DEF) {
O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0));
O << "\n";
return;
} else if (Opcode == PPC32::CALLpcrel) {
} else if (Opcode == PPC::CALLpcrel) {
O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0));
O << "\n";
return;
} else if (Opcode == PPC32::CALLindirect) {
} else if (Opcode == PPC::CALLindirect) {
O << TII.getName(Opcode) << " ";
printImmOp(MI->getOperand(0), ArgType[0]);
O << ", ";
printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n";
return;
} else if (Opcode == PPC32::MovePCtoLR) {
} else if (Opcode == PPC::MovePCtoLR) {
// FIXME: should probably be converted to cout.width and cout.fill
O << "bl \"L0000" << LabelNumber << "$pb\"\n";
O << "\"L0000" << LabelNumber << "$pb\":\n";
@ -545,34 +545,34 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
}
O << TII.getName(Opcode) << " ";
if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) {
printOp(MI->getOperand(0));
O << ", lo16(";
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")";
O << "(";
if (MI->getOperand(1).getReg() == PPC32::R0)
if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ")\n";
} else if (Opcode == PPC32::LOADHiAddr) {
} else if (Opcode == PPC::LOADHiAddr) {
printOp(MI->getOperand(0));
O << ", ";
if (MI->getOperand(1).getReg() == PPC32::R0)
if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ", ha16(" ;
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")\n";
} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
} else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
printOp(MI->getOperand(0));
O << ", ";
printImmOp(MI->getOperand(1), ArgType[1]);
O << "(";
if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC32::R0)
MI->getOperand(2).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(2));
@ -580,9 +580,9 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
} else {
for (i = 0; i < ArgCount; ++i) {
// addi and friends
if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
MI->getOperand(1).hasAllocatedReg() &&
MI->getOperand(1).getReg() == PPC32::R0) {
MI->getOperand(1).getReg() == PPC::R0) {
O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&

744
lib/Target/PowerPC/PowerPCISelSimple.cpp
View File

File diff suppressed because it is too large Load Diff

12
lib/Target/PowerPC/PowerPCInstrInfo.cpp
View File

@ -26,32 +26,32 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
if (oc == PPC32::OR) { // or r1, r2, r2
if (oc == PPC::OR) { // or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isRegister() &&
"invalid PPC32 OR instruction!");
"invalid PPC OR instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC32::ADDI) { // addi r1, r2, 0
} else if (oc == PPC::ADDI) { // addi r1, r2, 0
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC32 ADDI instruction!");
"invalid PPC ADDI instruction!");
if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC32::FMR) { // fmr r1, r2
} else if (oc == PPC::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid PPC32 FMR instruction");
"invalid PPC FMR instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;

16
lib/Target/PowerPC/PowerPCInstrInfo.h
View File

@ -20,7 +20,7 @@
namespace llvm {
namespace PPC32II {
namespace PPCII {
enum {
ArgCountShift = 0,
ArgCountMask = 7,
@ -83,13 +83,13 @@ public:
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC32 branch opcode!");
case PPC32::BEQ: return PPC32::BNE;
case PPC32::BNE: return PPC32::BEQ;
case PPC32::BLT: return PPC32::BGE;
case PPC32::BGE: return PPC32::BLT;
case PPC32::BGT: return PPC32::BLE;
case PPC32::BLE: return PPC32::BGT;
default: assert(0 && "Unknown PPC branch opcode!");
case PPC::BEQ: return PPC::BNE;
case PPC::BNE: return PPC::BEQ;
case PPC::BLT: return PPC::BGE;
case PPC::BGE: return PPC::BLT;
case PPC::BGT: return PPC::BLE;
case PPC::BLE: return PPC::BGT;
}
}
};

2
lib/Target/PowerPC/PowerPCPEI.cpp
View File

@ -170,7 +170,7 @@ void PPCPEI::calculateCallerSavedRegisters(MachineFunction &Fn) {
unsigned RegSize = RegInfo->getRegClass(RegsToSave[i])->getSize();
int FrameIdx;
if (RegsToSave[i] == PPC32::LR) {
if (RegsToSave[i] == PPC::LR) {
FrameIdx = FFI->CreateFixedObject(RegSize, 8); // LR lives at +8
} else {
Offset -= RegSize;

52
lib/Target/PowerPC/PowerPCRegisterInfo.cpp
View File

@ -31,8 +31,8 @@
using namespace llvm;
PowerPCRegisterInfo::PowerPCRegisterInfo()
: PowerPCGenRegisterInfo(PPC32::ADJCALLSTACKDOWN,
PPC32::ADJCALLSTACKUP) {}
: PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN,
PPC::ADJCALLSTACKUP) {}
static unsigned getIdx(const TargetRegisterClass *RC) {
if (RC == PowerPC::GPRCRegisterClass) {
@ -59,12 +59,12 @@ PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] = {
PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS, PPC32::STFD
PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
};
unsigned OC = Opcode[getIdx(RC)];
if (SrcReg == PPC32::LR) {
MBB.insert(MI, BuildMI(PPC32::MFLR, 0, PPC32::R0));
MBB.insert(MI, addFrameReference(BuildMI(OC,3).addReg(PPC32::R0),FrameIdx));
if (SrcReg == PPC::LR) {
MBB.insert(MI, BuildMI(PPC::MFLR, 0, PPC::R0));
MBB.insert(MI, addFrameReference(BuildMI(OC,3).addReg(PPC::R0),FrameIdx));
return 2;
} else {
MBB.insert(MI, addFrameReference(BuildMI(OC, 3).addReg(SrcReg),FrameIdx));
@ -78,12 +78,12 @@ PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] = {
PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS, PPC32::LFD
PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
};
unsigned OC = Opcode[getIdx(RC)];
if (DestReg == PPC32::LR) {
MBB.insert(MI, addFrameReference(BuildMI(OC, 2, PPC32::R0), FrameIdx));
MBB.insert(MI, BuildMI(PPC32::MTLR, 1).addReg(PPC32::R0));
if (DestReg == PPC::LR) {
MBB.insert(MI, addFrameReference(BuildMI(OC, 2, PPC::R0), FrameIdx));
MBB.insert(MI, BuildMI(PPC::MTLR, 1).addReg(PPC::R0));
return 2;
} else {
MBB.insert(MI, addFrameReference(BuildMI(OC, 2, DestReg), FrameIdx));
@ -98,9 +98,9 @@ int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineInstr *I;
if (RC == PowerPC::GPRCRegisterClass) {
I = BuildMI(PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
I = BuildMI(PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PowerPC::FPRCRegisterClass) {
I = BuildMI(PPC32::FMR, 1, DestReg).addReg(SrcReg);
I = BuildMI(PPC::FMR, 1, DestReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
@ -138,12 +138,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
Amount = (Amount+Align-1)/Align*Align;
MachineInstr *New;
if (Old->getOpcode() == PPC32::ADJCALLSTACKDOWN) {
New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
New = BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
.addSImm(-Amount);
} else {
assert(Old->getOpcode() == PPC32::ADJCALLSTACKUP);
New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
New = BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
.addSImm(Amount);
}
@ -168,7 +168,7 @@ PowerPCRegisterInfo::eliminateFrameIndex(MachineFunction &MF,
int FrameIndex = MI.getOperand(i).getFrameIndex();
// Replace the FrameIndex with base register with GPR1.
MI.SetMachineOperandReg(i, PPC32::R1);
MI.SetMachineOperandReg(i, PPC::R1);
// Take into account whether it's an add or mem instruction
unsigned OffIdx = (i == 2) ? 1 : 2;
@ -213,7 +213,7 @@ void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
// of the stack and round the size to a multiple of the alignment.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned Size = getRegClass(PPC32::R1)->getSize();
unsigned Size = getRegClass(PPC::R1)->getSize();
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
// Update frame info to pretend that this is part of the stack...
@ -221,18 +221,18 @@ void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// adjust stack pointer: r1 -= numbytes
if (NumBytes <= 32768) {
MI = BuildMI(PPC32::STWU, 3).addReg(PPC32::R1).addSImm(-NumBytes)
.addReg(PPC32::R1);
MI = BuildMI(PPC::STWU, 3).addReg(PPC::R1).addSImm(-NumBytes)
.addReg(PPC::R1);
MBB.insert(MBBI, MI);
} else {
int NegNumbytes = -NumBytes;
MI = BuildMI(PPC32::LIS, 1, PPC32::R0).addSImm(NegNumbytes >> 16);
MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
MBB.insert(MBBI, MI);
MI = BuildMI(PPC32::ORI, 2, PPC32::R0).addReg(PPC32::R0)
MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
.addImm(NegNumbytes & 0xFFFF);
MBB.insert(MBBI, MI);
MI = BuildMI(PPC32::STWUX, 3).addReg(PPC32::R1).addReg(PPC32::R1)
.addReg(PPC32::R0);
MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
.addReg(PPC::R0);
MBB.insert(MBBI, MI);
}
}
@ -242,14 +242,14 @@ void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;
assert(MBBI->getOpcode() == PPC32::BLR &&
assert(MBBI->getOpcode() == PPC::BLR &&
"Can only insert epilog into returning blocks");
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
if (NumBytes != 0) {
MI = BuildMI(PPC32::LWZ, 2, PPC32::R1).addSImm(0).addReg(PPC32::R1);
MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
MBB.insert(MBBI, MI);
}
}