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Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-03-26 09:52:32 +00:00
parent e506f9ae35
commit 5b6a01b59c
3 changed files with 6 additions and 34 deletions
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24
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -279,26 +279,6 @@ unsigned PPC::getVSPLTImmediate(SDNode *N) {
return cast<ConstantSDNode>(N->getOperand(0))->getValue(); return cast<ConstantSDNode>(N->getOperand(0))->getValue();
} }
/// isZeroVector - Return true if this build_vector is an all-zero vector.
///
bool PPC::isZeroVector(SDNode *N) {
if (MVT::isInteger(N->getOperand(0).getValueType())) {
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
if (!isa<ConstantSDNode>(N->getOperand(i)) ||
cast<ConstantSDNode>(N->getOperand(i))->getValue() != 0)
return false;
} else {
assert(MVT::isFloatingPoint(N->getOperand(0).getValueType()) &&
"Vector of non-int, non-float values?");
// See if this is all zeros.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
if (!isa<ConstantFPSDNode>(N->getOperand(i)) ||
!cast<ConstantFPSDNode>(N->getOperand(i))->isExactlyValue(0.0))
return false;
}
return true;
}
/// isVecSplatImm - Return true if this is a build_vector of constants which /// isVecSplatImm - Return true if this is a build_vector of constants which
/// can be formed by using a vspltis[bhw] instruction. The ByteSize field /// can be formed by using a vspltis[bhw] instruction. The ByteSize field
/// indicates the number of bytes of each element [124] -> [bhw]. /// indicates the number of bytes of each element [124] -> [bhw].
@ -347,7 +327,7 @@ bool PPC::isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val) {
int ShAmt = (4-ByteSize)*8; int ShAmt = (4-ByteSize)*8;
int MaskVal = ((int)Value << ShAmt) >> ShAmt; int MaskVal = ((int)Value << ShAmt) >> ShAmt;
// If this is zero, don't match, zero matches isZeroVector. // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
if (MaskVal == 0) return false; if (MaskVal == 0) return false;
if (Val) *Val = MaskVal; if (Val) *Val = MaskVal;
@ -721,7 +701,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// See if this is all zeros. // See if this is all zeros.
// FIXME: We should handle splat(-0.0), and other cases here. // FIXME: We should handle splat(-0.0), and other cases here.
if (PPC::isZeroVector(Op.Val)) if (ISD::isBuildVectorAllZeros(Op.Val))
return Op; return Op;
if (PPC::isVecSplatImm(Op.Val, 1) || // vspltisb if (PPC::isVecSplatImm(Op.Val, 1) || // vspltisb

4
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -102,10 +102,6 @@ namespace llvm {
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N); unsigned getVSPLTImmediate(SDNode *N);
/// isZeroVector - Return true if this build_vector is an all-zero vector.
///
bool isZeroVector(SDNode *N);
/// isVecSplatImm - Return true if this is a build_vector of constants which /// isVecSplatImm - Return true if this is a build_vector of constants which
/// can be formed by using a vspltis[bhw] instruction. The ByteSize field /// can be formed by using a vspltis[bhw] instruction. The ByteSize field
/// indicates the number of bytes of each element [124] -> [bhw]. /// indicates the number of bytes of each element [124] -> [bhw].

12
lib/Target/PowerPC/PPCInstrAltivec.td
View File

@ -24,10 +24,6 @@ def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isSplatShuffleMask(N); return PPC::isSplatShuffleMask(N);
}], VSPLT_get_imm>; }], VSPLT_get_imm>;
def vecimm0 : PatLeaf<(build_vector), [{
return PPC::isZeroVector(N);
}]>;
// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
@ -404,7 +400,7 @@ def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
"vxor $vD, $vD, $vD", VecFP, "vxor $vD, $vD, $vD", VecFP,
[(set VRRC:$vD, (v4f32 vecimm0))]>; [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -415,9 +411,9 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v16i8 vecimm0), (v16i8 (V_SET0))>; def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
def : Pat<(v8i16 vecimm0), (v8i16 (V_SET0))>; def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
def : Pat<(v4i32 vecimm0), (v4i32 (V_SET0))>; def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
// Loads. // Loads.
def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>; def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;