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* doxygenize comment

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* rename MachineFrameInfo to TargetFrameInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5170 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-12-28 20:13:29 +00:00
parent 5fa01b9c7a
commit 5b927c790e
1 changed files with 10 additions and 16 deletions
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26
include/llvm/Target/TargetMachine.h
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@ -14,7 +14,7 @@ class MachineInstrInfo;
class MachineInstrDescriptor; class MachineInstrDescriptor;
class MachineSchedInfo; class MachineSchedInfo;
class MachineRegInfo; class MachineRegInfo;
class MachineFrameInfo; class TargetFrameInfo;
class MachineCacheInfo; class MachineCacheInfo;
class MachineOptInfo; class MachineOptInfo;
class MachineCodeEmitter; class MachineCodeEmitter;
@ -22,19 +22,14 @@ class MRegisterInfo;
class PassManager; class PassManager;
class Pass; class Pass;
//--------------------------------------------------------------------------- //===----------------------------------------------------------------------===//
// class TargetMachine ///
// /// TargetMachine - Primary interface to the complete machine description for
// Purpose: /// the target machine. All target-specific information should be accessible
// Primary interface to the complete machine description for the /// through this interface.
// target machine. All target-specific information should be ///
// accessible through this interface.
//
//---------------------------------------------------------------------------
class TargetMachine : public NonCopyableV { class TargetMachine : public NonCopyableV {
const std::string Name; const std::string Name;
public:
const TargetData DataLayout; // Calculates type size & alignment const TargetData DataLayout; // Calculates type size & alignment
protected: protected:
@ -53,7 +48,6 @@ public:
const std::string &getName() const { return Name; } const std::string &getName() const { return Name; }
//
// Interfaces to the major aspects of target machine information: // Interfaces to the major aspects of target machine information:
// -- Instruction opcode and operand information // -- Instruction opcode and operand information
// -- Pipelines and scheduling information // -- Pipelines and scheduling information
@ -65,14 +59,14 @@ public:
virtual const MachineInstrInfo& getInstrInfo() const = 0; virtual const MachineInstrInfo& getInstrInfo() const = 0;
virtual const MachineSchedInfo& getSchedInfo() const = 0; virtual const MachineSchedInfo& getSchedInfo() const = 0;
virtual const MachineRegInfo& getRegInfo() const = 0; virtual const MachineRegInfo& getRegInfo() const = 0;
virtual const MachineFrameInfo& getFrameInfo() const = 0; virtual const TargetFrameInfo& getFrameInfo() const = 0;
virtual const MachineCacheInfo& getCacheInfo() const = 0; virtual const MachineCacheInfo& getCacheInfo() const = 0;
virtual const MachineOptInfo& getOptInfo() const = 0; virtual const MachineOptInfo& getOptInfo() const = 0;
const TargetData &getTargetData() const { return DataLayout; } const TargetData &getTargetData() const { return DataLayout; }
/// getRegisterInfo - If register information is available, return it. If /// getRegisterInfo - If register information is available, return it. If
/// not, return null. This is kept separate from RegInfo until RegInfo gets /// not, return null. This is kept separate from RegInfo until RegInfo has
/// straightened out. /// details of graph coloring register allocation removed from it.
/// ///
virtual const MRegisterInfo* getRegisterInfo() const { return 0; } virtual const MRegisterInfo* getRegisterInfo() const { return 0; }