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Emit comparisons against the sign bit better. Codegen this:

Browse Source 
bool %test1(long %X) {
        %A = setlt long %X, 0
        ret bool %A
}

like this:

test1:
        cmpl $0, 8(%esp)
        setl %al
        movzbl %al, %eax
        ret

instead of:

test1:
        movl 8(%esp), %ecx
        cmpl $0, %ecx
        setl %al
        movzbw %al, %ax
        cmpl $0, 4(%esp)
        setb %dl
        movzbw %dl, %dx
        cmpl $0, %ecx
        cmove %dx, %ax
        movzbl %al, %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-12 02:19:10 +00:00
parent 08b698e38d
commit 5b95ed652f
1 changed files with 10 additions and 0 deletions
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10
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -768,6 +768,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
DAG.getConstant(0, Tmp1.getValueType())); DAG.getConstant(0, Tmp1.getValueType()));
break; break;
default: default:
// If this is a comparison of the sign bit, just look at the top part.
// X > -1, x < 0
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
CST->getValue() == 0) || // X < 0
(cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
(CST->isAllOnesValue()))) // X > -1
return DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
Node->getValueType(0), LHSHi, RHSHi);
// FIXME: This generated code sucks. // FIXME: This generated code sucks.
ISD::CondCode LowCC; ISD::CondCode LowCC;
switch (cast<SetCCSDNode>(Node)->getCondition()) { switch (cast<SetCCSDNode>(Node)->getCondition()) {