Add definitions for the PPC a2q core marked as having QPX available

This is the first commit of a large series which will add support for the
QPX vector instruction set to the PowerPC backend. This instruction set is
used on the IBM Blue Gene/Q supercomputers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-01-30 21:17:42 +00:00
parent 2f89e8144b
commit 5bb16fdbb3
3 changed files with 19 additions and 0 deletions

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@ -58,6 +58,8 @@ def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
"Enable the isel instruction">;
def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
"Enable Book E instructions">;
def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
"Enable QPX instructions">;
//===----------------------------------------------------------------------===//
// Register File Description
@ -109,6 +111,11 @@ def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
FeatureSTFIWX, FeatureISEL,
Feature64Bit
/*, Feature64BitRegs */]>;
def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
FeatureMFOCRF, FeatureFSqrt,
FeatureSTFIWX, FeatureISEL,
Feature64Bit /*, Feature64BitRegs */,
FeatureQPX]>;
def : Processor<"pwr6", G5Itineraries,
[DirectivePwr6, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,

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@ -70,6 +70,7 @@ protected:
bool Use64BitRegs;
bool IsPPC64;
bool HasAltivec;
bool HasQPX;
bool HasFSQRT;
bool HasSTFIWX;
bool HasISEL;
@ -150,6 +151,7 @@ public:
bool hasFSQRT() const { return HasFSQRT; }
bool hasSTFIWX() const { return HasSTFIWX; }
bool hasAltivec() const { return HasAltivec; }
bool hasQPX() const { return HasQPX; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool isBookE() const { return IsBookE; }

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@ -0,0 +1,10 @@
; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
; RUN: llc < %s -march=ppc64 -mcpu=a2 -mattr=+qpx | FileCheck %s
define void @foo() {
entry:
ret void
}
; CHECK: @foo