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Add definitions for the PPC a2q core marked as having QPX available
This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,6 +58,8 @@ def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions">;
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def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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"Enable QPX instructions">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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@ -109,6 +111,11 @@ def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureSTFIWX, FeatureISEL,
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Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureMFOCRF, FeatureFSqrt,
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FeatureSTFIWX, FeatureISEL,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureQPX]>;
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def : Processor<"pwr6", G5Itineraries,
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[DirectivePwr6, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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@ -70,6 +70,7 @@ protected:
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bool Use64BitRegs;
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bool IsPPC64;
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bool HasAltivec;
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bool HasQPX;
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bool HasFSQRT;
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bool HasSTFIWX;
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bool HasISEL;
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@ -150,6 +151,7 @@ public:
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bool hasFSQRT() const { return HasFSQRT; }
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bool hasSTFIWX() const { return HasSTFIWX; }
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bool hasAltivec() const { return HasAltivec; }
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bool hasQPX() const { return HasQPX; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool isBookE() const { return IsBookE; }
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10
test/CodeGen/PowerPC/a2q.ll
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10
test/CodeGen/PowerPC/a2q.ll
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@ -0,0 +1,10 @@
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; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
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; RUN: llc < %s -march=ppc64 -mcpu=a2 -mattr=+qpx | FileCheck %s
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define void @foo() {
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entry:
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ret void
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}
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; CHECK: @foo
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