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https://github.com/c64scene-ar/llvm-6502.git
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Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
parent
6a907f8c7d
commit
5c042162be
@ -885,6 +885,7 @@ enum {
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R_MICROMIPS_HI16 = 134,
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R_MICROMIPS_LO16 = 135,
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R_MICROMIPS_GOT16 = 138,
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R_MICROMIPS_PC16_S1 = 141,
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R_MICROMIPS_CALL16 = 142,
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R_MICROMIPS_GOT_DISP = 145,
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R_MICROMIPS_GOT_PAGE = 146,
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@ -165,6 +165,7 @@ StringRef getELFRelocationTypeName(uint32_t Machine, uint32_t Type) {
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_HI16);
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_LO16);
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_GOT16);
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_PC16_S1);
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_CALL16);
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_GOT_DISP);
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LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MICROMIPS_GOT_PAGE);
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@ -205,6 +205,13 @@ static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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// DecodeJumpTargetMM - Decode microMIPS jump target, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
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@ -751,6 +758,16 @@ static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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unsigned BranchOffset = Offset & 0xffff;
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BranchOffset = SignExtend32<18>(BranchOffset << 1);
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -84,6 +84,10 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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case Mips::fixup_MICROMIPS_26_S1:
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Value >>= 1;
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break;
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case Mips::fixup_MICROMIPS_PC16_S1:
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Value -= 4;
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Value >>= 1;
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break;
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}
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return Value;
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@ -201,6 +205,7 @@ public:
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{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
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{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
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@ -195,6 +195,9 @@ unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target,
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case Mips::fixup_MICROMIPS_GOT16:
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Type = ELF::R_MICROMIPS_GOT16;
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break;
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case Mips::fixup_MICROMIPS_PC16_S1:
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Type = ELF::R_MICROMIPS_PC16_S1;
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break;
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case Mips::fixup_MICROMIPS_CALL16:
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Type = ELF::R_MICROMIPS_CALL16;
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break;
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@ -140,6 +140,9 @@ namespace Mips {
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// resulting in - R_MICROMIPS_GOT16
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fixup_MICROMIPS_GOT16,
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// resulting in - R_MICROMIPS_PC16_S1
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fixup_MICROMIPS_PC16_S1,
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// resulting in - R_MICROMIPS_CALL16
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fixup_MICROMIPS_CALL16,
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@ -96,6 +96,12 @@ public:
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unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getMachineOpValue - Return binary encoding of operand. If the machin
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// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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@ -276,6 +282,28 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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return 0;
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}
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/// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// If the destination is an immediate, divide by 2.
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if (MO.isImm()) return MO.getImm() >> 1;
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assert(MO.isExpr() &&
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"getBranchTargetOpValueMM expects only expressions or immediates");
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const MCExpr *Expr = MO.getExpr();
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Fixups.push_back(MCFixup::Create(0, Expr,
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MCFixupKind(Mips::
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fixup_MICROMIPS_PC16_S1)));
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return 0;
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}
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/// getJumpTargetOpValue - Return binary encoding of the jump
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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@ -238,3 +238,40 @@ class JALR_FM_MM<bits<10> funct> : MMArch {
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let Inst{15-6} = funct;
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let Inst{5-0} = 0x3c;
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}
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class BEQ_FM_MM<bits<6> op> : MMArch {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = offset;
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}
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class BGEZ_FM_MM<bits<5> funct> : MMArch {
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 0x10;
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let Inst{25-21} = funct;
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let Inst{20-16} = rs;
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let Inst{15-0} = offset;
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}
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class BGEZAL_FM_MM<bits<5> funct> : MMArch {
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 0x10;
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let Inst{25-21} = funct;
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let Inst{20-16} = rs;
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let Inst{15-0} = offset;
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}
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@ -20,6 +20,12 @@ def calltarget_mm : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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def brtarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValueMM";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTargetMM";
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}
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let canFoldAsLoad = 1 in
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class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd> :
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@ -177,4 +183,22 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def TAILCALL_R_MM : MMRel, JumpFR<"tcallr", GPR32Opnd, MipsTailCall>,
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JR_FM_MM<0x3c>, IsTailCall;
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def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
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/// Branch Instructions
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def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
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BEQ_FM_MM<0x25>;
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def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
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BEQ_FM_MM<0x2d>;
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def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
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BGEZ_FM_MM<0x2>;
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def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
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BGEZ_FM_MM<0x6>;
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def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
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BGEZ_FM_MM<0x4>;
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def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
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BGEZ_FM_MM<0x0>;
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def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x03>;
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def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x01>;
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}
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@ -151,12 +151,12 @@ def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
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/// Jump and Branch Instructions
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let isCodeGenOnly = 1 in {
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def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
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def BEQ64 : CBranch<"beq", seteq, GPR64Opnd>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", setne, GPR64Opnd>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", setge, GPR64Opnd>, BGEZ_FM<1, 1>;
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def BGTZ64 : CBranchZero<"bgtz", setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", setle, GPR64Opnd>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
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def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
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def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
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def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
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def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
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def TAILCALL64_R : JumpFR<"tcallr", GPR64Opnd, MipsTailCall>,
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@ -106,6 +106,8 @@ private:
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unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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@ -194,6 +196,12 @@ unsigned MipsCodeEmitter::getJumpTargetOpValueMM(const MachineInstr &MI,
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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MachineOperand MO = MI.getOperand(OpNo);
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@ -272,7 +272,7 @@ class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
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let Inst{5-0} = funct;
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}
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class BEQ_FM<bits<6> op> {
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class BEQ_FM<bits<6> op> : StdArch {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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@ -285,7 +285,7 @@ class BEQ_FM<bits<6> op> {
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let Inst{15-0} = offset;
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}
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class BGEZ_FM<bits<6> op, bits<5> funct> {
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class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
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bits<5> rs;
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bits<16> offset;
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@ -389,7 +389,7 @@ class JALR_FM : StdArch {
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let Inst{5-0} = 9;
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}
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class BGEZAL_FM<bits<5> funct> {
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class BGEZAL_FM<bits<5> funct> : StdArch {
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bits<5> rs;
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bits<16> offset;
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@ -504,21 +504,24 @@ class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
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}
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// Conditional Branch
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class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
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class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
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RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
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!strconcat(opstr, "\t$rs, $rt, $offset"),
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[(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
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FrmI> {
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FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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}
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class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, brtarget:$offset),
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class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
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RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, opnd:$offset),
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!strconcat(opstr, "\t$rs, $offset"),
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[(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
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[(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
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FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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@ -602,9 +605,9 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in {
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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[], IIBranch, FrmR, opstr>;
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class BGEZAL_FT<string opstr, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, brtarget:$offset),
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!strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
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class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, opnd:$offset),
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!strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
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}
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@ -994,19 +997,23 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
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def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
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Requires<[RelocStatic, HasStdEnc]>, IsBranch;
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def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
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def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
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def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
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def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
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def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
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def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
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def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
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def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
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def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
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def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
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BGEZ_FM<1, 1>;
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def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
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BGEZ_FM<7, 0>;
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def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
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BGEZ_FM<6, 0>;
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def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
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BGEZ_FM<1, 0>;
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def B : UncondBranch<BEQ>;
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def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
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def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
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def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
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def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
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def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
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def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
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def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
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def TAILCALL : MMRel, JumpFJ<calltarget, "j", MipsTailCall, imm, "tcall">,
|
||||
FJ<2>, IsTailCall;
|
||||
|
||||
@ -225,3 +225,27 @@
|
||||
|
||||
# CHECK: jr $7
|
||||
0x00 0x07 0x0f 0x3c
|
||||
|
||||
# CHECK: beq $9, $6, 1332
|
||||
0x94 0xc9 0x02 0x9a
|
||||
|
||||
# CHECK: bgez $6, 1332
|
||||
0x40 0x46 0x02 0x9a
|
||||
|
||||
# CHECK: bgezal $6, 1332
|
||||
0x40 0x66 0x02 0x9a
|
||||
|
||||
# CHECK: bltzal $6, 1332
|
||||
0x40 0x26 0x02 0x9a
|
||||
|
||||
# CHECK: bgtz $6, 1332
|
||||
0x40 0xc6 0x02 0x9a
|
||||
|
||||
# CHECK: blez $6, 1332
|
||||
0x40 0x86 0x02 0x9a
|
||||
|
||||
# CHECK: bne $9, $6, 1332
|
||||
0xb4 0xc9 0x02 0x9a
|
||||
|
||||
# CHECK: bltz $6, 1332
|
||||
0x40 0x06 0x02 0x9a
|
||||
|
||||
@ -225,3 +225,27 @@
|
||||
|
||||
# CHECK: jr $7
|
||||
0x07 0x00 0x3c 0x0f
|
||||
|
||||
# CHECK: beq $9, $6, 1332
|
||||
0xc9 0x94 0x9a 0x02
|
||||
|
||||
# CHECK: bgez $6, 1332
|
||||
0x46 0x40 0x9a 0x02
|
||||
|
||||
# CHECK: bgezal $6, 1332
|
||||
0x66 0x40 0x9a 0x02
|
||||
|
||||
# CHECK: bltzal $6, 1332
|
||||
0x26 0x40 0x9a 0x02
|
||||
|
||||
# CHECK: bgtz $6, 1332
|
||||
0xc6 0x40 0x9a 0x02
|
||||
|
||||
# CHECK: blez $6, 1332
|
||||
0x86 0x40 0x9a 0x02
|
||||
|
||||
# CHECK: bne $9, $6, 1332
|
||||
0xc9 0xb4 0x9a 0x02
|
||||
|
||||
# CHECK: bltz $6, 1332
|
||||
0x06 0x40 0x9a 0x02
|
||||
|
||||
65
test/MC/Mips/micromips-branch-instructions.s
Normal file
65
test/MC/Mips/micromips-branch-instructions.s
Normal file
@ -0,0 +1,65 @@
|
||||
# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
|
||||
# RUN: | FileCheck %s -check-prefix=CHECK-EL
|
||||
# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
|
||||
# RUN: | FileCheck %s -check-prefix=CHECK-EB
|
||||
# Check that the assembler can handle the documented syntax
|
||||
# for arithmetic and logical instructions.
|
||||
#------------------------------------------------------------------------------
|
||||
# Branch Instructions
|
||||
#------------------------------------------------------------------------------
|
||||
# Little endian
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-EL: b 1332 # encoding: [0x00,0x94,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: beq $9, $6, 1332 # encoding: [0xc9,0x94,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bgez $6, 1332 # encoding: [0x46,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bgezal $6, 1332 # encoding: [0x66,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bltzal $6, 1332 # encoding: [0x26,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bgtz $6, 1332 # encoding: [0xc6,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: blez $6, 1332 # encoding: [0x86,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bne $9, $6, 1332 # encoding: [0xc9,0xb4,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bal 1332 # encoding: [0x60,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EL: bltz $6, 1332 # encoding: [0x06,0x40,0x9a,0x02]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
#------------------------------------------------------------------------------
|
||||
# Big endian
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-EB: b 1332 # encoding: [0x94,0x00,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: beq $9, $6, 1332 # encoding: [0x94,0xc9,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bgez $6, 1332 # encoding: [0x40,0x46,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bgezal $6, 1332 # encoding: [0x40,0x66,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bltzal $6, 1332 # encoding: [0x40,0x26,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bgtz $6, 1332 # encoding: [0x40,0xc6,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: blez $6, 1332 # encoding: [0x40,0x86,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bne $9, $6, 1332 # encoding: [0xb4,0xc9,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bal 1332 # encoding: [0x40,0x60,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-EB: bltz $6, 1332 # encoding: [0x40,0x06,0x02,0x9a]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
b 1332
|
||||
beq $9,$6,1332
|
||||
bgez $6,1332
|
||||
bgezal $6,1332
|
||||
bltzal $6,1332
|
||||
bgtz $6,1332
|
||||
blez $6,1332
|
||||
bne $9,$6,1332
|
||||
bal 1332
|
||||
bltz $6,1332
|
||||
69
test/MC/Mips/micromips-branch16.s
Normal file
69
test/MC/Mips/micromips-branch16.s
Normal file
@ -0,0 +1,69 @@
|
||||
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \
|
||||
# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
|
||||
# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \
|
||||
# RUN: -mattr=micromips | llvm-readobj -r \
|
||||
# RUN: | FileCheck %s -check-prefix=CHECK-ELF
|
||||
#------------------------------------------------------------------------------
|
||||
# Check that the assembler can handle the documented syntax
|
||||
# for relocations.
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-FIXUP: b bar # encoding: [A,0x94'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: beq $3, $4, bar # encoding: [0x83'A',0x94'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: bne $3, $4, bar # encoding: [0x83'A',0xb4'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: bgez $4, bar # encoding: [0x44'A',0x40'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: bgtz $4, bar # encoding: [0xc4'A',0x40'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: blez $4, bar # encoding: [0x84'A',0x40'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: bltz $4, bar # encoding: [0x04'A',0x40'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: bgezal $4, bar # encoding: [0x64'A',0x40'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-FIXUP: bltzal $4, bar # encoding: [0x24'A',0x40'A',0x00,0x00]
|
||||
# CHECK-FIXUP: # fixup A - offset: 0,
|
||||
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1
|
||||
# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
#------------------------------------------------------------------------------
|
||||
# Check that the appropriate relocations were created.
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-ELF: Relocations [
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1
|
||||
# CHECK-ELF: ]
|
||||
|
||||
b bar
|
||||
beq $3, $4, bar
|
||||
bne $3, $4, bar
|
||||
bgez $4, bar
|
||||
bgtz $4, bar
|
||||
blez $4, bar
|
||||
bltz $4, bar
|
||||
bgezal $4, bar
|
||||
bltzal $4, bar
|
||||
Loading…
Reference in New Issue
Block a user