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Make sure that the register is in the register class before adding it as a machine op.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2011-10-14 23:55:44 +00:00
parent 969c9ef0dd
commit 5d79859f66
1 changed files with 3 additions and 1 deletions
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4
lib/Target/ARM/ARMISelLowering.cpp
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@ -5921,9 +5921,11 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
MachineInstrBuilder MIB(&*II);
for (unsigned i = 0; SavedRegs[i] != 0; ++i)
for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
if (!TRC->contains(SavedRegs[i])) continue;
if (!DefRegs[SavedRegs[i]])
MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define);
}
break;
}