From 5d79859f66fa1540d5a1c1e9e4f4e080e6e956f1 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 14 Oct 2011 23:55:44 +0000 Subject: [PATCH] Make sure that the register is in the register class before adding it as a machine op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f3bc719450f..f1000de429f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5921,9 +5921,11 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { MachineInstrBuilder MIB(&*II); - for (unsigned i = 0; SavedRegs[i] != 0; ++i) + for (unsigned i = 0; SavedRegs[i] != 0; ++i) { + if (!TRC->contains(SavedRegs[i])) continue; if (!DefRegs[SavedRegs[i]]) MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define); + } break; }