From 5d8aa345dd8f92d572a3c639ee7c6f5a7a932384 Mon Sep 17 00:00:00 2001
From: Eric Christopher <echristo@apple.com>
Date: Thu, 30 Jun 2011 00:48:30 +0000
Subject: [PATCH] Fix a small thinko for constant i64 lock/orq optimization
where we we didn't have an opcode for 64-bit constant or expressions.
Fixes rdar://9692967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Target/X86/X86ISelDAGToDAG.cpp | 6 ++++--
test/CodeGen/X86/atomic-or.ll | 18 ++++++++++++++++++
2 files changed, 22 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/X86/atomic-or.ll
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 1fcc274e0f8..15c19177056 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1612,16 +1612,18 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
Opc = AtomicOpcTbl[Op][I32];
break;
case MVT::i64:
+ Opc = AtomicOpcTbl[Op][I64];
if (isCN) {
if (immSext8(Val.getNode()))
Opc = AtomicOpcTbl[Op][SextConstantI64];
else if (i64immSExt32(Val.getNode()))
Opc = AtomicOpcTbl[Op][ConstantI64];
- } else
- Opc = AtomicOpcTbl[Op][I64];
+ }
break;
}
+ assert(Opc != 0 && "Invalid arith lock transform!");
+
DebugLoc dl = Node->getDebugLoc();
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, NVT), 0);
diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
new file mode 100644
index 00000000000..cd622908aca
--- /dev/null
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; rdar://9692967
+
+define void @do_the_sync(i64* %p, i32 %b) nounwind {
+entry:
+ %p.addr = alloca i64*, align 8
+ store i64* %p, i64** %p.addr, align 8
+ %tmp = load i64** %p.addr, align 8
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+; CHECK: lock
+; CHECK-NEXT: orq $2147483648
+ %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ ret void
+}
+declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind