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Delete the 'standard' spiller with used the old spilling framework.
The current register allocators all use the inline spiller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144477 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -29,7 +29,7 @@
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using namespace llvm;
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using namespace llvm;
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namespace {
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namespace {
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enum SpillerName { trivial, standard, inline_ };
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enum SpillerName { trivial, inline_ };
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}
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}
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static cl::opt<SpillerName>
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static cl::opt<SpillerName>
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@ -37,10 +37,9 @@ spillerOpt("spiller",
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cl::desc("Spiller to use: (default: standard)"),
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cl::desc("Spiller to use: (default: standard)"),
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cl::Prefix,
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cl::Prefix,
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cl::values(clEnumVal(trivial, "trivial spiller"),
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cl::values(clEnumVal(trivial, "trivial spiller"),
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clEnumVal(standard, "default spiller"),
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clEnumValN(inline_, "inline", "inline spiller"),
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clEnumValN(inline_, "inline", "inline spiller"),
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clEnumValEnd),
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clEnumValEnd),
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cl::init(standard));
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cl::init(trivial));
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// Spiller virtual destructor implementation.
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// Spiller virtual destructor implementation.
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Spiller::~Spiller() {}
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Spiller::~Spiller() {}
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@ -188,54 +187,12 @@ public:
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} // end anonymous namespace
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} // end anonymous namespace
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namespace {
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/// Falls back on LiveIntervals::addIntervalsForSpills.
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class StandardSpiller : public Spiller {
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protected:
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MachineFunction *mf;
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LiveIntervals *lis;
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LiveStacks *lss;
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MachineLoopInfo *loopInfo;
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VirtRegMap *vrm;
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public:
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StandardSpiller(MachineFunctionPass &pass, MachineFunction &mf,
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VirtRegMap &vrm)
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: mf(&mf),
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lis(&pass.getAnalysis<LiveIntervals>()),
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lss(&pass.getAnalysis<LiveStacks>()),
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loopInfo(pass.getAnalysisIfAvailable<MachineLoopInfo>()),
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vrm(&vrm) {}
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/// Falls back on LiveIntervals::addIntervalsForSpills.
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void spill(LiveRangeEdit &LRE) {
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std::vector<LiveInterval*> added =
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lis->addIntervalsForSpills(LRE.getParent(), LRE.getUselessVRegs(),
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loopInfo, *vrm);
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LRE.getNewVRegs()->insert(LRE.getNewVRegs()->end(),
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added.begin(), added.end());
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// Update LiveStacks.
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int SS = vrm->getStackSlot(LRE.getReg());
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if (SS == VirtRegMap::NO_STACK_SLOT)
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return;
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const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
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LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
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if (!SI.hasAtLeastOneValue())
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SI.getNextValue(SlotIndex(), 0, lss->getVNInfoAllocator());
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SI.MergeRangesInAsValue(LRE.getParent(), SI.getValNumInfo(0));
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}
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};
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} // end anonymous namespace
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llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
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llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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MachineFunction &mf,
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VirtRegMap &vrm) {
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VirtRegMap &vrm) {
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switch (spillerOpt) {
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switch (spillerOpt) {
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default: assert(0 && "unknown spiller");
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default: assert(0 && "unknown spiller");
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case trivial: return new TrivialSpiller(pass, mf, vrm);
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case trivial: return new TrivialSpiller(pass, mf, vrm);
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case standard: return new StandardSpiller(pass, mf, vrm);
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case inline_: return createInlineSpiller(pass, mf, vrm);
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case inline_: return createInlineSpiller(pass, mf, vrm);
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}
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}
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}
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -verify-machineinstrs -spiller=standard
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; RUN: llc < %s -verify-machineinstrs -spiller=trivial
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; RUN: llc < %s -verify-machineinstrs -spiller=inline
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; RUN: llc < %s -verify-machineinstrs -spiller=inline
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; PR8612
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; PR8612
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;
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;
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