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[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223515 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
2014-12-05 21:09:27 +00:00
parent 86af53ecf0
commit 5db47f1376
5 changed files with 86 additions and 46 deletions
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8
test/MC/Disassembler/Hexagon/alu32_perm.txt
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@@ -10,6 +10,14 @@
# CHECK: r17 = combine(r31.l, r21.l)
0xb0 0xe2 0x0f 0x7c
# CHECK: r17:16 = combine(#21, #31)
0xf1 0xc3 0x75 0x73
# CHECK: r17 = mux(p3, r21, #31)
0xb1 0xc2 0xff 0x73
# CHECK: r17 = mux(p3, #21, r31)
0xb1 0xe2 0x8f 0x7b
# CHECK: r17 = mux(p3, #21, #31)
0x71 0xdf 0x15 0xf4
# CHECK: r17 = mux(p3, r21, r31)
0x11 0xc0 0x15 0x70
# CHECK: r17 = aslh(r21)
0x11 0xc0 0x35 0x70