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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228326 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
ec35069525
commit
5e00f0d72d
@ -774,7 +774,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
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DistSR = End->getSubReg();
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} else {
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const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
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(RegToImm ? TII->get(Hexagon::SUB_ri) :
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(RegToImm ? TII->get(Hexagon::A2_subri) :
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TII->get(Hexagon::A2_addi));
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unsigned SubR = MRI->createVirtualRegister(IntRC);
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MachineInstrBuilder SubIB =
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@ -391,15 +391,13 @@ multiclass Addri_Pred<string mnemonic, bit PredNot> {
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}
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}
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let isExtendable = 1, InputType = "imm" in
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let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
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multiclass Addri_base<string mnemonic, SDNode OpNode> {
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let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
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let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
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isPredicable = 1 in
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let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
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def A2_#NAME : T_Addri<s16Ext>;
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let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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hasSideEffects = 0, isPredicated = 1 in {
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let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
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defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
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defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
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}
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@ -438,17 +436,15 @@ class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
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let Inst{4-0} = Rd;
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}
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def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
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def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
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def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
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def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
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// Subtract register from immediate
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// Rd32=sub(#s10,Rs32)
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
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CextOpcode = "sub", InputType = "imm", hasNewValue = 1 in
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def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
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"$Rd = sub(#$s10, $Rs)" ,
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[(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
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ImmRegRel {
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let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
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opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
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def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
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"$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
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bits<5> Rd;
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bits<10> s10;
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bits<5> Rs;
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@ -468,9 +464,13 @@ def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
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let IClass = 0b0111;
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let Inst{27-24} = 0b1111;
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}
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def: Pat<(sub s10ExtPred:$s10, IntRegs:$Rs),
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(A2_subri imm:$s10, IntRegs:$Rs)>;
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// Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
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def : Pat<(not (i32 IntRegs:$src1)),
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(SUB_ri -1, (i32 IntRegs:$src1))>;
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def: Pat<(not (i32 IntRegs:$src1)),
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(A2_subri -1, IntRegs:$src1)>;
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let hasSideEffects = 0, hasNewValue = 1 in
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class T_tfr16<bit isHi>
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@ -712,8 +712,8 @@ def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1, opNewValue = 0 in
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class T_ALU32_2op <string mnemonic, bits<3> minOp> :
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ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = "#mnemonic#"($Rs)", [] > {
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ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = "#mnemonic#"($Rs)", [] > {
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bits<5> Rd;
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bits<5> Rs;
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@ -732,11 +732,11 @@ class T_ALU32_2op <string mnemonic, bits<3> minOp> :
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, validSubTargets = HasV4SubT,
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hasNewValue = 1, opNewValue = 0 in
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class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
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bit isPredNew > :
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ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
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!if(isPredNot, "if (!$Pu", "if ($Pu")
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#!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
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class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
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bit isPredNew > :
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ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
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!if(isPredNot, "if (!$Pu", "if ($Pu")
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#!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
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bits<5> Rd;
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bits<2> Pu;
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bits<5> Rs;
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@ -816,7 +816,6 @@ multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
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}
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}
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let isCodeGenOnly=0 in
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defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
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def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
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@ -997,7 +996,8 @@ def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
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//===----------------------------------------------------------------------===//
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// ALU64/ALU +
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//===----------------------------------------------------------------------===//// Add.
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//===----------------------------------------------------------------------===//
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// Add.
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//===----------------------------------------------------------------------===//
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// Template Class
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// Add/Subtract halfword
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@ -1394,7 +1394,7 @@ def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
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//===----------------------------------------------------------------------===//
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def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
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def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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@ -1404,7 +1404,7 @@ class CondStr<string CReg, bit True, bit New> {
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string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
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}
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class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
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string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
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string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", ""));
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}
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let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
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@ -1442,7 +1442,7 @@ class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
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let Inst{27-24} = 0b1100;
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let Inst{21} = PredNot;
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let Inst{12} = !if(isPredNew, isTak, zero);
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let Inst{12} = isTak;
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let Inst{11} = isPredNew;
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let Inst{9-8} = src;
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let Inst{23-22} = dst{16-15};
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@ -1452,7 +1452,7 @@ class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
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}
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multiclass JMP_Pred<bit PredNot, string ExtStr> {
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def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
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def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken
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// Predicate new
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def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
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def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
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@ -1499,13 +1499,13 @@ class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
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let Inst{27-22} = 0b001101;
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let Inst{21} = PredNot;
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let Inst{20-16} = dst;
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let Inst{12} = !if(isPredNew, isTak, zero);
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let Inst{12} = isTak;
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let Inst{11} = isPredNew;
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let Inst{9-8} = src;
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}
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multiclass JMPR_Pred<bit PredNot> {
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def NAME: T_JMPr_c<PredNot, 0, 0>;
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def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
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// Predicate new
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def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
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def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
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@ -1609,7 +1609,7 @@ class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
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!if (!eq(ImmOpStr, "s11_2Ext"), 13,
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!if (!eq(ImmOpStr, "s11_1Ext"), 12,
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/* s11_0Ext */ 11)));
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let hasNewValue = !if (!eq(ImmOpStr, "s11_3Ext"), 0, 1);
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let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
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let IClass = 0b1001;
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@ -1739,7 +1739,7 @@ let AddedComplexity = 20 in {
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// do the trick.
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let AddedComplexity = 20 in
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def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
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(SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
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(A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
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//===----------------------------------------------------------------------===//
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// Post increment load
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@ -649,23 +649,23 @@ def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
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* ALU32/ALU *
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*********************************************************************/
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def : T_RR_pat<A2_add, int_hexagon_A2_add>;
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def : T_RI_pat<A2_addi, int_hexagon_A2_addi>;
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def : T_RI_pat<A2_addi, int_hexagon_A2_addi>;
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def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
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def : T_IR_pat<SUB_ri, int_hexagon_A2_subri>;
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def : T_IR_pat<A2_subri, int_hexagon_A2_subri>;
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def : T_RR_pat<A2_and, int_hexagon_A2_and>;
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def : T_RI_pat<AND_ri, int_hexagon_A2_andir>;
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def : T_RI_pat<A2_andir, int_hexagon_A2_andir>;
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def : T_RR_pat<A2_or, int_hexagon_A2_or>;
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def : T_RI_pat<OR_ri, int_hexagon_A2_orir>;
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def : T_RI_pat<A2_orir, int_hexagon_A2_orir>;
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def : T_RR_pat<A2_xor, int_hexagon_A2_xor>;
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def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
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// Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
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def : Pat <(int_hexagon_A2_not (I32:$Rs)),
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(SUB_ri -1, IntRegs:$Rs)>;
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(A2_subri -1, IntRegs:$Rs)>;
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// Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
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def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
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(SUB_ri 0, IntRegs:$Rs)>;
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(A2_subri 0, IntRegs:$Rs)>;
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// Transfer immediate
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def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
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