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Fix bug while building FP16 constant vectors for AArch64

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Summary: Building FP16 constant vectors caused the FP16 data to be bitcast to i64.  This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling.

Reviewers: mcrosier

Reviewed By: mcrosier

Subscribers: mcrosier, jmolloy, ab, srhines, llvm-commits, rengolin, aemerson

Differential Revision: http://reviews.llvm.org/D8369

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232562 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pirama Arumuga Nainar 2015-03-17 23:10:29 +00:00
parent f99fa6d5fd
commit 5e15d64948
2 changed files with 13 additions and 2 deletions
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6
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -5892,8 +5892,10 @@ FailedModImm:
if (VT.getVectorElementType().isFloatingPoint()) {
SmallVector<SDValue, 8> Ops;
MVT NewType =
(VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
EVT EltTy = VT.getVectorElementType();
assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
"Unsupported floating-point vector type");
MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
for (unsigned i = 0; i < NumElts; ++i)
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);

9
test/CodeGen/AArch64/fp16-v4-instructions.ll
View File

@ -12,6 +12,15 @@ entry:
}
define <4 x half> @build_h4(<4 x half> %a) {
entry:
; CHECK-LABEL: build_h4:
; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd
; CHECK: dup v0.4h, [[GPR]]
ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
}
define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
entry:
; CHECK-LABEL: sub_h: